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    • 1. 发明授权
    • Low power high speed pipeline ADC
    • 低功耗高速流水线ADC
    • US08451160B1
    • 2013-05-28
    • US13109320
    • 2011-05-17
    • Hao ZhouYonghua SongTao ShuiJie JiangSong Chen
    • Hao ZhouYonghua SongTao ShuiJie JiangSong Chen
    • H03M1/38
    • H03M1/002H03M1/1215H03M1/124H03M1/167
    • In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved. A multiplying analog to digital converter (MDAC) circuit receives the time-interleaved first and second sample voltages from the first and second passive sampling circuits and processes the time-interleaved first and second sample voltages to generate a residue output voltage.
    • 根据本文描述的教导,为时间交错流水线模数转换器提供了系统和方法。 示例性管线模数转换器可以包括无源采样电路和乘法数模转换器电路。 第一无源采样电路包括耦合到模拟输入信号的输入端,并且输出响应于模拟输入信号的第一采样电压。 第二无源采样电路包括耦合到模拟输入信号的输入端,并且输出响应于模拟输入信号的第二采样电压。 第一和第二无源采样电路被计时,使得第一采样电压和第二采样电压是时间交织的。 乘法模数转换器(MDAC)电路接收来自第一和第二无源采样电路的时间交错的第一和第二采样电压,并处理时间交错的第一和第二采样电压以产生残余输出电压。
    • 2. 发明授权
    • Voltage reference buffer using voltage battery level shifter
    • 电压参考缓冲器使用电压电池电平转换器
    • US09190859B1
    • 2015-11-17
    • US13115813
    • 2011-05-25
    • Hao ZhouYonghua SongTao ShuiJie Jiang
    • Hao ZhouYonghua SongTao ShuiJie Jiang
    • H02J7/00
    • H03K17/161H02J7/0054H03K17/063H03K2217/0081
    • In one embodiment, an apparatus includes a first supply voltage and a second supply voltage. Level shifter circuitry is configured as a first voltage battery to shift a first voltage and a second voltage battery to shift a second voltage. A first circuit receives the shifted first voltage and sets a third voltage, and receives the shifted second voltage and sets a fourth voltage. The shifted first voltage is greater than the first supply voltage and the shifted second voltage level is less than the second supply voltage. A second circuit sets a fifth voltage and a sixth voltage. The fifth voltage follows the third voltage and the sixth voltage following the fourth voltage.
    • 在一个实施例中,装置包括第一电源电压和第二电源电压。 电平移位器电路被配置为第一电压电池以移动第一电压和第二电压电池以移位第二电压。 第一电路接收移位的第一电压并设置第三电压,并接收移位的第二电压并设置第四电压。 移位的第一电压大于第一电源电压,并且移位的第二电压电平小于第二电源电压。 第二电路设置第五电压和第六电压。 第五电压跟随第四电压的第三电压和第六电压。
    • 5. 发明授权
    • Low-jitter phase-locked loop
    • 低抖动锁相环
    • US07990225B1
    • 2011-08-02
    • US12498989
    • 2009-07-07
    • Jianmin GuoYihui LiHong XueYonghua SongTao ShuiHao Zhou
    • Jianmin GuoYihui LiHong XueYonghua SongTao ShuiHao Zhou
    • H03L7/085
    • H03L7/099H03L7/093H03L2207/06
    • A phase-locked loop (PLL) with a decreased frequency tuning gain KVCO and a loop filter using capacitor multiplication technique to get high chip area efficiency. To get decreased frequency tuning gain, KVCO, a voltage to current converter in a voltage-controlled oscillator (VCO) in the PLL may comprise a first voltage to current converter and a second voltage to current converter. The trans-conductance of the first voltage to current converter is 1/β of that of the second voltage to current converter, wherein β>1. The first voltage to current converter is controlled by an output voltage of a loop filter in the PLL, and the second voltage to current converter is controlled by a relative DC voltage, which may be the junction node between R1 and C1 in a loop filer of the PLL. Capacitor multiplication technique may use an auxiliary charge pump to charge or discharge the junction node between R1 and C1 inversely to the main charge pump. When the charge or discharge current unit of the auxiliary charge pump is α times of the main charge pump, the capacitance of C1 may be reduced to just (1−α) times of what it needed in a conventional loop stability compensation method, wherein α
    • 具有降低的频率调谐增益KVCO的锁相环(PLL)和使用电容器乘法技术的环路滤波器以获得高芯片面积效率。 为了降低频率调谐增益,PLL中的压控振荡器(VCO)中的电压 - 电流转换器KVCO可以包括第一电压 - 电流转换器和第二电压 - 电流转换器。 第一个电压到电流转换器的反向电导为1 / 的第二电压到电流转换器,其中&amp; 1。 第一个电压到电流转换器由PLL中的环路滤波器的输出电压控制,第二个电压到电流转换器由一个相对直流电压控制,相对直流电压可以是一个环路滤波器中的R1和C1之间的结点 PLL。 电容倍增技术可以使用辅助电荷泵来将R1和C1之间的连接节点与主电荷泵反向充电或放电。 当辅助电荷泵的充电或放电电流单元是主电荷泵的α倍时,C1的电容可以降低到常规环路稳定性补偿方法中所需要的(1-α)倍,其中α <1。
    • 10. 发明授权
    • High sensitivity GLONASS/GPS automatic frequency control
    • 高灵敏度GLONASS / GPS自动频率控制
    • US08754809B2
    • 2014-06-17
    • US13041312
    • 2011-03-04
    • Hao ZhouHao-Jen ChengQinfang Sun
    • Hao ZhouHao-Jen ChengQinfang Sun
    • G01S19/24G01S19/21G01S19/29
    • G01S19/29
    • Updates to an AFC loop can be performed to provide high-sensitivity tracking. A 20 ms update interval and PDI=10 ms is used for every other update. A setting is used for each update between the 20 ms updates. Notably, the setting uses PDI=5 ms. The setting can include first, second, and third cross-dot pairs associated with a first bit, a second bit, and a cross-bit boundary between the first and second bits, respectively. A sum of these pairs can be scaled down when the signal strength is below a predetermined threshold. In another embodiment, the setting can include a first cross-dot pair associated with a first bit and a second cross-dot pair associated with a second bit. A sum of these pairs can also be scaled down when signal strength is below a predetermined threshold.
    • 可以执行AFC循环的更新以提供高灵敏度跟踪。 每隔一个更新使用20 ms的更新间隔和PDI = 10 ms。 每个20 ms更新之间的更新使用一个设置。 值得注意的是,该设置使用PDI = 5 ms。 该设置可以分别包括与第一位,第二位和第一和第二位之间的跨位边界相关联的第一,第二和第三十字点对。 当信号强度低于预定阈值时,这些对的总和可以缩小。 在另一个实施例中,该设置可以包括与第一位相关联的第一交叉点对和与第二位相关联的第二交叉点对。 当信号强度低于预定阈值时,这些对的总和也可以缩小。