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41. 发明授权

US07721174B2 Full-speed BIST controller for testing embedded synchronous memories 有权
标题翻译：全速BIST控制器用于测试嵌入式同步存储器
公开(公告)号：US07721174B2
公开(公告)日：2010-05-18
申请号：US10985539
申请日：2004-11-09
申请人： Wu-Tung Cheng , Christopher John Hill , Omar Kebichi
发明人： Wu-Tung Cheng , Christopher John Hill , Omar Kebichi
IPC分类号： G01R31/28 , G01R29/00
CPC分类号： G11C29/16 , G11C29/14 , G11C29/50
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译：公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。

42. 发明授权

US07487419B2 Reduced-pin-count-testing architectures for applying test patterns 有权
标题翻译：用于应用测试模式的减少针数测试架构
公开(公告)号：US07487419B2
公开(公告)日：2009-02-03
申请号：US11305849
申请日：2005-12-16
申请人： Nilanjan Mukherjee , Jay Jahangiri , Ronald Press , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Jay Jahangiri , Ronald Press , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318572 , G01R31/318583
摘要： Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.
摘要翻译：公开了使用一个或多个边界扫描单元测试集成电路的方法，装置和系统。方法，装置和系统可以用于例如通过一个或多个边界扫描单元应用速度测试图案。例如，在一个示例性非限制性实施例中，公开了一种电路，其包括耦合到被测电路的主输入端口或主输出端口的一个或多个边界扫描单元。电路还包括配置成将测试控制信号施加到一个或多个边界扫描单元的边界扫描单元控制器。在该实施例中，控制器被配置为在操作模式下操作，由此控制器将测试控制信号施加到对应于用于控制电路的一个或多个内部扫描链的测试控制信号的一个或多个边界扫描单元测试中测试。该示例性实施例的控制信号包括在边界扫描单元控制器之外产生的一个速度 - 时钟信号。

43. 发明授权

US07296249B2 Using constrained scan cells to test integrated circuits 有权
标题翻译：使用受限扫描单元测试集成电路
公开(公告)号：US07296249B2
公开(公告)日：2007-11-13
申请号：US10961760
申请日：2004-10-07
申请人： Thomas Hans Rinderknecht , Wu-Tung Cheng
发明人： Thomas Hans Rinderknecht , Wu-Tung Cheng
IPC分类号： G06F17/50 , G06F11/00 , G01R31/28
CPC分类号： G01R31/318547
摘要： Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed.
摘要翻译：公开了用于测试集成电路的各种新的和非显而易见的装置和方法。在一个示例性实施例中，在集成电路设计中选择控制点。识别集成电路设计中的扫描单元，其可以加载一组固定值，以将期望的测试值传播到控制点。集成电路设计被修改为包括配置成在测试阶段期间以集合的固定值在集成电路设计中加载扫描单元的电路组件。可以通过将控制点对准扫描单元来识别一个或多个扫描单元，从而确定扫描单元必须输出的值，以便将控制点驱动到期望的测试值。还公开了包括计算机可执行指令的计算机可读介质，所述计算机可执行指令用于使计算机执行任何所公开的方法或任何所公开的设备的计算机可读设计信息。

44. 发明申请

US20060156133A1 Flexible memory built-in-self-test (MBIST) method and apparatus 有权
标题翻译：灵活内存内置自检（MBIST）方法和装置
公开(公告)号：US20060156133A1
公开(公告)日：2006-07-13
申请号：US11282938
申请日：2005-11-18
申请人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要： Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译：公开了可编程存储器内置的自检（MBIST）方法，装置和系统。所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。

45. 发明申请

US20050066247A1 Full-speed BIST controller for testing embedded synchronous memories 有权
标题翻译：全速BIST控制器用于测试嵌入式同步存储器
公开(公告)号：US20050066247A1
公开(公告)日：2005-03-24
申请号：US10985539
申请日：2004-11-09
申请人： Wu-Tung Cheng , Christopher Hill , Omar Kebichi
发明人： Wu-Tung Cheng , Christopher Hill , Omar Kebichi
IPC分类号： G11C29/14 , G11C29/16 , G11C29/50 , G01R31/28
CPC分类号： G11C29/16 , G11C29/14 , G11C29/50
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译：公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。

46. 发明授权

US06829728B2 Full-speed BIST controller for testing embedded synchronous memories 有权
标题翻译：全速BIST控制器用于测试嵌入式同步存储器
公开(公告)号：US06829728B2
公开(公告)日：2004-12-07
申请号：US09800092
申请日：2001-03-05
申请人： Wu-Tung Cheng , Christopher John Hill , Omar Kebichi
发明人： Wu-Tung Cheng , Christopher John Hill , Omar Kebichi
IPC分类号： G06F1100
CPC分类号： G11C29/16 , G11C29/14 , G11C29/50
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译：公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。

47. 发明授权

US06456961B1 Method and apparatus for creating testable circuit designs having embedded cores 有权
标题翻译：用于创建具有嵌入式核心的可测试电路设计的方法和装置
公开(公告)号：US06456961B1
公开(公告)日：2002-09-24
申请号：US09302699
申请日：1999-04-30
申请人： Srinivas Patil , Wu-Tung Cheng , Paul J. Reuter
发明人： Srinivas Patil , Wu-Tung Cheng , Paul J. Reuter
IPC分类号： G06F1750
CPC分类号： G01R31/318505
摘要： A computer-implemented method and apparatus for creating a testable circuit design that includes one or more embedded cores. The method includes identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design. The method further includes providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design. The cores within the circuit design can then be tested after manufacture by applying the design test vectors to the circuit design.
摘要翻译：一种用于创建包括一个或多个嵌入式核心的可测试电路设计的计算机实现的方法和装置。该方法包括识别电路设计内的嵌入式核心; 将嵌入式核心的某些引脚与电路设计的引脚相关联; 并将插入到嵌入式芯的某些连接引脚的电路设计访问电路插入电路设计的相关引脚。该方法还包括提供用于嵌入式核心的测试向量; 以及通过将适用于嵌入式核心的某些引脚的核心测试向量映射到电路设计的相关引脚来生成用于电路设计的测试向量。然后可以通过将设计测试矢量应用于电路设计，然后在制造后对电路设计中的核心进行测试。

48. 发明授权

US08843796B2 Profiling-based scan chain diagnosis 有权
标题翻译：基于分析的扫描链诊断
公开(公告)号：US08843796B2
公开(公告)日：2014-09-23
申请号：US13158743
申请日：2011-06-13
申请人： Wu-Tung Cheng , Yu Huang
发明人： Wu-Tung Cheng , Yu Huang
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3183
CPC分类号： G01R31/318569 , G01R31/318342 , G01R31/318544
摘要： With various implementations of the invention, unloading masking information for each of the scan patterns is first determined. A tester then applies the scan patterns to a circuit under test and collects test response data according to the unloading masking information. A profiling-based analysis is performed to determine failing scan cell information based on the test response data.
摘要翻译：利用本发明的各种实施方式，首先确定每个扫描模式的卸载掩蔽信息。然后，测试仪将扫描图案应用于被测电路，并根据卸载屏蔽信息收集测试响应数据。执行基于分析的分析，以基于测试响应数据确定故障扫描单元信息。

49. 发明授权

US08689070B2 Method and system for scan chain diagnosis 有权
标题翻译：扫描链诊断方法与系统
公开(公告)号：US08689070B2
公开(公告)日：2014-04-01
申请号：US12781695
申请日：2010-05-17
申请人： Yu Huang , Wu-Tung Cheng , Ruifeng Guo , Ting-Pu Tai
发明人： Yu Huang , Wu-Tung Cheng , Ruifeng Guo , Ting-Pu Tai
IPC分类号： G06F11/00
CPC分类号： G01R31/318544 , G01R31/318547 , G06F11/2215
摘要： Scan chain diagnosis techniques are disclosed. Faulty scan chains are modeled and scan patterns are masked to filter out loading-caused failures. By simulating the masked scan patterns, failing probabilities are determined for cells on a faulty scan chain. One or more defective cells are identified based upon the failing probability information. A noise filtering system such as the one based upon adaptive feedback may be adopted for the identification process.
摘要翻译：公开扫描链诊断技术。对扫描链进行建模和扫描模式被屏蔽，以过滤掉加载引起的故障。通过模拟掩蔽的扫描模式，确定故障扫描链上的单元的故障概率。基于故障概率信息来识别一个或多个有缺陷的小区。可以采用诸如基于自适应反馈的噪声滤波系统来进行识别处理。

50. 发明申请

US20120216088A1 GENERATING TEST SETS FOR DIAGNOSING SCAN CHAIN FAILURES 有权
标题翻译：生成用于诊断扫描链失败的测试集
公开(公告)号：US20120216088A1
公开(公告)日：2012-08-23
申请号：US13460407
申请日：2012-04-30
申请人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
发明人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318525 , G01R31/31853 , G01R31/318533 , G01R31/318544 , G01R31/318569
摘要： Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
摘要翻译：所公开技术的实施例包括可用于改进扫描链测试模式生成和扫描链故障诊断解析的基于软件的技术。例如，某些实施例可用于产生能够将扫描链缺陷隔离成单个扫描单元的高质量链诊断测试图案。这样的实施例可用于产生“完整”测试集，即，能够将故障扫描链中的任何扫描链缺陷分离到单个扫描单元的一组链诊断测试模式。

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