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1. 发明授权

US07424660B2 Synchronization point across different memory BIST controllers 有权
标题翻译：跨不同内存BIST控制器的同步点
公开(公告)号：US07424660B2
公开(公告)日：2008-09-09
申请号：US11397822
申请日：2006-04-03
申请人： Omar Kebichi , Wu-Tung Cheng , Christopher John Hill , Paul J. Reuter , Yahya M. Z. Mustafa
发明人： Omar Kebichi , Wu-Tung Cheng , Christopher John Hill , Paul J. Reuter , Yahya M. Z. Mustafa
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/12015 , G11C29/14 , G11C29/56012 , G11C2029/0401 , G11C2029/2602
摘要： A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.
摘要翻译：公开了一种用于使用嵌入在集成电路（IC）中的多个内置自测（BIST）控制器测试存储器的电路。通过允许同步状态，BIST控制器在存储器测试期间被带到同步点。来自IC上的输出引脚的输出信号表示存在与自动测试设备（ATE）的同步状态。 ATE接收到输出信号后，通过IC输入引脚发出一个恢复信号，导致控制器进入同步状态。 ATE通过延迟恢复信号来控制同步状态长度。同步状态可用于参数化测试算法，例如保留和IDDQ测试。可以通过软件设计工具将同步状态并入用户定义的算法，该工具可生成可操作以将同步状态应用于算法的BIST控制器的HDL描述。

2. 发明授权

US07721174B2 Full-speed BIST controller for testing embedded synchronous memories 有权
标题翻译：全速BIST控制器用于测试嵌入式同步存储器
公开(公告)号：US07721174B2
公开(公告)日：2010-05-18
申请号：US10985539
申请日：2004-11-09
申请人： Wu-Tung Cheng , Christopher John Hill , Omar Kebichi
发明人： Wu-Tung Cheng , Christopher John Hill , Omar Kebichi
IPC分类号： G01R31/28 , G01R29/00
CPC分类号： G11C29/16 , G11C29/14 , G11C29/50
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译：公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。

3. 发明授权

US06829728B2 Full-speed BIST controller for testing embedded synchronous memories 有权
标题翻译：全速BIST控制器用于测试嵌入式同步存储器
公开(公告)号：US06829728B2
公开(公告)日：2004-12-07
申请号：US09800092
申请日：2001-03-05
申请人： Wu-Tung Cheng , Christopher John Hill , Omar Kebichi
发明人： Wu-Tung Cheng , Christopher John Hill , Omar Kebichi
IPC分类号： G06F1100
CPC分类号： G11C29/16 , G11C29/14 , G11C29/50
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译：公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。

4. 发明授权

US07036064B1 Synchronization point across different memory BIST controllers 有权
公开(公告)号：US07036064B1
公开(公告)日：2006-04-25
申请号：US09872212
申请日：2001-05-31
申请人： Omar Kebichi , Wu-Tung Cheng , Christopher John Hill , Paul J. Reuter , Yahya M. Z. Mustafa
发明人： Omar Kebichi , Wu-Tung Cheng , Christopher John Hill , Paul J. Reuter , Yahya M. Z. Mustafa
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/12015 , G11C29/14 , G11C29/56012 , G11C2029/0401 , G11C2029/2602
摘要： A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.

5. 发明申请

US20050066247A1 Full-speed BIST controller for testing embedded synchronous memories 有权
标题翻译：全速BIST控制器用于测试嵌入式同步存储器
公开(公告)号：US20050066247A1
公开(公告)日：2005-03-24
申请号：US10985539
申请日：2004-11-09
申请人： Wu-Tung Cheng , Christopher Hill , Omar Kebichi
发明人： Wu-Tung Cheng , Christopher Hill , Omar Kebichi
IPC分类号： G11C29/14 , G11C29/16 , G11C29/50 , G01R31/28
CPC分类号： G11C29/16 , G11C29/14 , G11C29/50
摘要： A test circuit is disclosed for testing embedded synchronous memories. A BIST controller is used to address the memory and provide reference data that is compared to the memory output. Pipeline registers are used to allow the BIST controller to perform reads and/or writes during every clock cycle. In one aspect, the BIST controller includes a reference data circuit that stores or generates data for comparison to the memory output. A pipeline register is positioned before the reference data circuit or between the reference data circuit and compare circuitry. Additional pipeline registers may be positioned between a compare capture circuit and the compare circuitry. The pipeline registers free the BIST controller from having to wait for a read to complete before starting the next read or write. To reduce the number of pipeline registers needed, a negative-edge BIST controller can be used with a positive-edge memory or vice versa.
摘要翻译：公开了一种用于测试嵌入式同步存储器的测试电路。 BIST控制器用于寻址存储器并提供与存储器输出进行比较的参考数据。流水线寄存器用于允许BIST控制器在每个时钟周期内执行读取和/或写操作。在一个方面，BIST控制器包括参考数据电路，其存储或产生用于与存储器输出进行比较的数据。流水线寄存器位于参考数据电路之前或参考数据电路和比较电路之间。另外的流水线寄存器可以位于比较捕捉电路和比较电路之间。流水线注册使得BIST控制器在开始下一次读取或写入之前不必等待读取完成。为了减少所需的流水线寄存器数量，负边缘BIST控制器可以与正边沿存储器一起使用，反之亦然。

6. 发明申请

US20060190789A1 Synchronization point across different memory BIST controllers 有权
标题翻译：跨不同内存BIST控制器的同步点
公开(公告)号：US20060190789A1
公开(公告)日：2006-08-24
申请号：US11397822
申请日：2006-04-03
申请人： Omar Kebichi , Wu-Tung Cheng , Christopher Hill , Paul Reuter , Yahya Mustafa
发明人： Omar Kebichi , Wu-Tung Cheng , Christopher Hill , Paul Reuter , Yahya Mustafa
IPC分类号： G01R31/28
CPC分类号： G11C29/12015 , G11C29/14 , G11C29/56012 , G11C2029/0401 , G11C2029/2602
摘要： A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.
摘要翻译：公开了一种用于使用嵌入在集成电路（IC）中的多个内置自测（BIST）控制器测试存储器的电路。通过允许同步状态，BIST控制器在存储器测试期间被带到同步点。来自IC上的输出引脚的输出信号表示存在与自动测试设备（ATE）的同步状态。 ATE接收到输出信号后，通过IC输入引脚发出一个恢复信号，导致控制器进入同步状态。 ATE通过延迟恢复信号来控制同步状态长度。同步状态可用于参数化测试算法，例如保留和IDDQ测试。软件设计工具可以将同步状态并入用户定义的算法，该工具可生成可操作以将同步状态应用于算法的BIST控制器的HDL描述。

7. 发明授权

US06671843B1 Method for providing user definable algorithms in memory BIST 有权
标题翻译：在存储器BIST中提供用户可定义算法的方法
公开(公告)号：US06671843B1
公开(公告)日：2003-12-30
申请号：US09737620
申请日：2000-12-14
申请人： Omar Kebichi , Christopher John Hill , Paul J. Reuter , Ian Alexander Burgess
发明人： Omar Kebichi , Christopher John Hill , Paul J. Reuter , Ian Alexander Burgess
IPC分类号： G01R3128
CPC分类号： G11C29/10 , G11C29/16 , G11C29/50
摘要： A method performed by a software design tool for providing an algorithm to a BIST controller that tests memory within a circuit. The method includes reading a description of a user defined test algorithm for a BIST controller, translating the description into an in-memory representation of the user defined algorithm, and reading a memory model selected by a user. The in-memory representation of the user-defined algorithm is associated with the selected memory model. From the association an HDL description of a BIST controller is generated. The HDL description is operable to apply the user defined algorithm to a memory corresponding to the selected memory model.
摘要翻译：由软件设计工具执行的方法，用于向BIST控制器提供测试电路内的存储器的算法。该方法包括读取用于BIST控制器的用户定义的测试算法的描述，将描述转换成用户定义算法的存储器内表示，以及读取由用户选择的存储器模型。用户定义的算法的内存中的表示与所选择的存储器模型相关联。从关联中生成BIST控制器的HDL描述。 HDL描述可操作以将用户定义的算法应用于对应于所选存储器模型的存储器。

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