专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070011542A1 Reduced-pin-count-testing architectures for applying test patterns 有权
标题翻译：用于应用测试模式的减少针数测试架构
公开(公告)号：US20070011542A1
公开(公告)日：2007-01-11
申请号：US11305849
申请日：2005-12-16
申请人： Nilanjan Mukherjee , Jay Jahangiri , Ronald Press , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Jay Jahangiri , Ronald Press , Wu-Tung Cheng
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318541 , G01R31/318572 , G01R31/318583
摘要： Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.
摘要翻译：公开了使用一个或多个边界扫描单元测试集成电路的方法，装置和系统。方法，装置和系统可以用于例如通过一个或多个边界扫描单元应用速度测试图案。例如，在一个示例性非限制性实施例中，公开了一种电路，其包括耦合到被测电路的主输入端口或主输出端口的一个或多个边界扫描单元。电路还包括配置成将测试控制信号施加到一个或多个边界扫描单元的边界扫描单元控制器。在该实施例中，控制器被配置为在操作模式下操作，由此控制器将测试控制信号施加到与用于控制电路的一个或多个内部扫描链的测试控制信号相对应的一个或多个边界扫描单元测试中测试。该示例性实施例的控制信号包括在边界扫描单元控制器之外产生的一个速度 - 时钟信号。

2. 发明授权

US07487419B2 Reduced-pin-count-testing architectures for applying test patterns 有权
标题翻译：用于应用测试模式的减少针数测试架构
公开(公告)号：US07487419B2
公开(公告)日：2009-02-03
申请号：US11305849
申请日：2005-12-16
申请人： Nilanjan Mukherjee , Jay Jahangiri , Ronald Press , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Jay Jahangiri , Ronald Press , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318572 , G01R31/318583
摘要： Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.
摘要翻译：公开了使用一个或多个边界扫描单元测试集成电路的方法，装置和系统。方法，装置和系统可以用于例如通过一个或多个边界扫描单元应用速度测试图案。例如，在一个示例性非限制性实施例中，公开了一种电路，其包括耦合到被测电路的主输入端口或主输出端口的一个或多个边界扫描单元。电路还包括配置成将测试控制信号施加到一个或多个边界扫描单元的边界扫描单元控制器。在该实施例中，控制器被配置为在操作模式下操作，由此控制器将测试控制信号施加到对应于用于控制电路的一个或多个内部扫描链的测试控制信号的一个或多个边界扫描单元测试中测试。该示例性实施例的控制信号包括在边界扫描单元控制器之外产生的一个速度 - 时钟信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式