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41. 发明授权

US06717846B1 Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration 有权
标题翻译：具有镜像在虚拟接地配置中的分离门存储器单元的非易失性半导体存储器
公开(公告)号：US06717846B1
公开(公告)日：2004-04-06
申请号：US09696085
申请日：2000-10-26
申请人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
发明人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
IPC分类号： G11C1616
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0491 , H01L27/115
摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. The cells are crased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.
摘要翻译：在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。使用Fowler-Nordheim，通过在浮栅的壁上形成的多晶硅氧化物，利用Fowler-Nordheim将浮动栅极的电子隧穿到控制栅极进行电池堆积。

42. 发明授权

US06563742B1 Method to turn a flash memory into a versatile, low-cost multiple time programmable EPROM 有权
标题翻译：将闪存转换成多功能，低成本多时间可编程EPROM的方法
公开(公告)号：US06563742B1
公开(公告)日：2003-05-13
申请号：US10090356
申请日：2002-03-04
申请人： Peter W. Lee , Tam H. Tran
发明人： Peter W. Lee , Tam H. Tran
IPC分类号： G11C1600
CPC分类号： G11C16/3409 , G11C16/0408 , G11C16/16 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： A multiple time programmable (MTP) memory device is achieved. The device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. The memory cell array comprises, preferably, a Flash memory cell array. A package has an external pin configuration that conforms to the JEDEC standard for an EPROM device wherein an external, positive programming voltage (VPP) pin is provided. Finally, an external, negative erasing voltage (VNN) pin is provided. The VNN pin is, preferably, multiplexed with the chip enable bar (CEB) pin.
摘要翻译：实现了多时间可编程（MTP）存储器件。该装置首先包括一个包括电可擦除性和电可编程性的装置的存储单元阵列。存储单元阵列优选地包括闪存单元阵列。封装具有符合EPROM器件的JEDEC标准的外部引脚配置，其中提供外部正的编程电压（VPP）引脚。最后，提供一个外部负的擦除电压（VNN）引脚。 VNN引脚优选地与芯片使能条（CEB）引脚复用。

43. 再颁专利

USRE37419E1 Flash memory array and decoding architecture 有权
标题翻译：闪存阵列和解码架构
公开(公告)号：USRE37419E1
公开(公告)日：2001-10-23
申请号：US09430060
申请日：1999-10-29
申请人： Fu-Change Hsu , Hsing-Ya Tsao , Peter W. Lee
发明人： Fu-Change Hsu , Hsing-Ya Tsao , Peter W. Lee
IPC分类号： G11C1604
CPC分类号： G11C11/5621 , G11C8/14 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3445 , G11C2211/5621 , H01L27/115
摘要： A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and a verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing. Several different approaches are presented for the layout of source segment control lines and transistors as well as the word lines.
摘要翻译：闪存电路包括具有偶数和奇数字线锁存器的字线解码器和具有源极线锁存器的源极线解码器。字线解码器和源极线解码器提供同时擦除闪存中的两个相邻字线的存储单元的能力，并且逐字地验证存储单元字。通过同时擦除两个相邻行，本发明的实施例消除了与常规闪存电路相关的过度擦除和源干扰问题。解码架构提供了可能从一对到大量多对字线的灵活的擦除大小。通过将字线的存储单元划分成多个段并具有由源段控制线和晶体管控制的分段源极线，解码电路还提供选择用于擦除的字线段的存储单元的能力。对于源段控制线和晶体管以及字线的布局提出了几种不同的方法。

44. 发明授权

US6009022A Node-precise voltage regulation for a MOS memory system 有权
标题翻译：用于MOS存储器系统的节点精确电压调节
公开(公告)号：US6009022A
公开(公告)日：1999-12-28
申请号：US189109
申请日：1998-11-09
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C16/30 , G11C7/00
CPC分类号： G11C7/12 , G11C16/30 , G11C5/147 , G11C8/08
摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.
摘要翻译：片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压。位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较差分输出比较器。用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

45. 发明授权

US5835420A Node-precise voltage regulation for a MOS memory system 失效
标题翻译：用于MOS存储器系统的节点精确电压调节
公开(公告)号：US5835420A
公开(公告)日：1998-11-10
申请号：US884251
申请日：1997-06-27
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C16/30 , G11C7/00
CPC分类号： G11C7/12 , G11C16/30 , G11C5/147 , G11C8/08
摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from at least one of which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.
摘要翻译：片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压中的至少一个。位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较差分输出比较器。用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

46. 发明授权

US5682350A Flash memory with divided bitline 失效
标题翻译：闪存分频线
公开(公告)号：US5682350A
公开(公告)日：1997-10-28
申请号：US726670
申请日：1996-10-07
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines, the drains of flash transistors in each column are coupled to common metal 1 lines divided into even metal 1 lines and odd metal 1 lines and the sources of the flash transistors are coupled to a common sourceline. A set of first selection transistors are coupled between even metal 1 lines and metal 2 lines having a pitch twice that of said metal 1 lines and controlled by a first select signal to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistors are coupled between odd metal 1 lines and the metal 2 lines and controlled by a second select signal to selectively couple the odd metal 1 lines to the metal 2 lines. In one embodiment, the set of first selection transistors and the set of second selection transistors are large in comparison to the flash transistors. Advantages of the invention include improved selection of memory cells, higher memory cell density and lower resistance in the memory cell selection circuitry.
摘要翻译：闪速存储器包括形成多行和多列的闪存晶体管组，每个闪存晶体管具有栅极，漏极和源极，其中每行中的闪存晶体管的栅极耦合到公共字线，闪存的漏极每列中的晶体管耦合到分为偶数金属1线和奇数金属1线的公共金属1线，并且闪存晶体管的源耦合到公共源极线。一组第一选择晶体管耦合在偶数金属1线和金属2线之间，金属2线具有两倍于所述金属1线的间距，并由第一选择信号控制，以选择性地将偶数金属1线耦合到金属2线。一组第二选择晶体管耦合在奇数金属1线和金属2线之间，并由第二选择信号控制，以将奇数金属1线选择性地耦合到金属2线。在一个实施例中，与闪存晶体管相比，该组第一选择晶体管和该组第二选择晶体管较大。本发明的优点包括存储器单元的改进选择，更高的存储单元密度和较低的存储单元选择电路中的电阻。

47. 发明授权

US5354387A Boron phosphorus silicate glass composite layer on semiconductor wafer 失效
标题翻译：硼硅酸玻璃复合层在半导体晶圆上
公开(公告)号：US5354387A
公开(公告)日：1994-10-11
申请号：US935951
申请日：1992-08-25
申请人： Peter W. Lee , David N. K. Wang , Makoto Nagashima , Kazuto Fukuma , Tetsuya Sato
发明人： Peter W. Lee , David N. K. Wang , Makoto Nagashima , Kazuto Fukuma , Tetsuya Sato
IPC分类号： C23C16/40 , H01L21/316 , H01L23/29 , H01L23/31 , H01L23/532 , H01L29/12 , H01L21/00 , H01L21/02 , H01L21/302
CPC分类号： H01L21/02129 , C23C16/401 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02343 , H01L21/31625 , H01L23/291 , H01L23/3171 , H01L23/5329 , H01L2924/0002 , Y10S148/118
摘要： A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dopants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.
摘要翻译：通过新的两步法在半导体晶片的台阶表面上形成复合BPSG绝缘和平坦化层。复合BPSG层的特征在于在随后的蚀刻步骤中不存在可辨别的空隙和耐受硼损失的表面。两步沉积工艺包括通过使用磷和硼掺杂剂的气态源和原硅酸四乙酯（TEOS）作为硅源的CVD沉积来形成无空隙的BPSG层的第一步骤; 然后第二步骤，通过等离子体辅助CVD沉积工艺形成BPSG的覆盖层，同时再次使用磷和硼掺杂物的气体源和TEOS作为硅源，以提供具有表面的BPSG盖层通过随后的蚀刻，不吸湿并且耐硼损失。

48. 发明授权

US5166101A Method for forming a boron phosphorus silicate glass composite layer on a semiconductor wafer 失效
标题翻译：在半导体晶片上形成硼硅酸玻璃复合层的方法
公开(公告)号：US5166101A
公开(公告)日：1992-11-24
申请号：US649172
申请日：1991-02-01
申请人： Peter W. Lee , David N. K. Wang , Makoto Nagashima , Kazuto Fukuma , Tetsuya Sato
发明人： Peter W. Lee , David N. K. Wang , Makoto Nagashima , Kazuto Fukuma , Tetsuya Sato
IPC分类号： C23C16/40 , H01L21/316 , H01L23/29 , H01L23/31 , H01L23/532
CPC分类号： H01L21/02129 , C23C16/401 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02343 , H01L21/31625 , H01L23/291 , H01L23/3171 , H01L23/5329 , H01L2924/0002 , Y10S148/118
摘要： A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dpoants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.
摘要翻译：通过新的两步法在半导体晶片的台阶表面上形成复合BPSG绝缘和平坦化层。复合BPSG层的特征在于在随后的蚀刻步骤中不存在可辨别的空隙和耐受硼损失的表面。两步沉积工艺包括通过使用磷和硼掺杂剂的气态源和原硅酸四乙酯（TEOS）作为硅源的CVD沉积来形成无空隙的BPSG层的第一步骤; 然后第二步骤，通过等离子体辅助CVD沉积工艺形成BPSG的覆盖层，同时再次使用磷和硼的气体源和TEOS作为硅源，以提供具有表面的BPSG盖层通过随后的蚀刻，不吸湿并且耐硼损失。

49. 发明授权

US4721598A Powder metal composite and method of its manufacture 失效
标题翻译：粉末金属复合材料及其制造方法
公开(公告)号：US4721598A
公开(公告)日：1988-01-26
申请号：US011751
申请日：1987-02-06
申请人： Peter W. Lee
发明人： Peter W. Lee
IPC分类号： B22F7/06 , B22F7/00
CPC分类号： B22F7/06 , Y10T428/1209 , Y10T428/12097
摘要： A powder metal composite made up of first and second powder metal bodies assembled in a mold cavity with the bodies separated by a divider ring and with the bodies being in concentric relationship such that the assembled bodies and divider ring can be simultaneously compacted and subsequently simultaneously sintered to form the desired composite metal article. In practicing the method of forming a composite metal article one of the bodies may be selected from a base powder metal and the other body may be selected from a high performance alloy powder metal, and the divider ring may be selected from a low melting point metal such as copper that will dissolve itself into the powders during sintering and enhance mechanical properties of the sintered compact article. The composital metal article may be used as it is if the density for its intended uses is satisfactory, or such article may be further densified by being subjected to an additional hot forging operation with the article sintered thereafter if deemed necessary.

50. 发明申请

US20110051524A1 Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device 失效
标题翻译：用于操作NAND类双电荷保持晶体管NOR闪存器件的方法和装置
公开(公告)号：US20110051524A1
公开(公告)日：2011-03-03
申请号：US12806848
申请日：2010-08-23
申请人： Fu-Chang Hsu , Peter W. Lee
发明人： Fu-Chang Hsu , Peter W. Lee
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0458 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C16/3477 , G11C2211/5621
摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.
摘要翻译：用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。

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