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41. 发明授权

US07141860B2 LDMOS transistor 有权
标题翻译： LDMOS晶体管
公开(公告)号：US07141860B2
公开(公告)日：2006-11-28
申请号：US10875105
申请日：2004-06-23
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/95 , H01L29/47
CPC分类号： H01L29/782 , H01L27/0727 , H01L29/0619 , H01L29/0653 , H01L29/47 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.
摘要翻译： LDMOS晶体管具有插入在LDMOS晶体管的掺杂区域的中心处的肖特基二极管。典型的LDMOS晶体管在中心具有漂移区域。在这种情况下，肖特基二极管被插入该漂移区的中心，其具有在正向上提供从源极到漏极连接的肖特基二极管的作用，使得漏极电压被钳位到低于PN结的电压阈值，从而避免正向偏置PN结。一种替代方案是将肖特基二极管插入其中形成源的阱，其位于LDMOS晶体管的外围。在这种情况下，肖特基二极管的形成方式不同，但仍然在正向方向上从源极到漏极连接，以在漏极处实现所需的电压钳位。

42. 发明授权

US07071518B2 Schottky device 失效
标题翻译：肖特基装置
公开(公告)号：US07071518B2
公开(公告)日：2006-07-04
申请号：US10856602
申请日：2004-05-28
申请人： Vijay Parthasarathy , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose
发明人： Vijay Parthasarathy , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/772
CPC分类号： H01L27/0727 , H01L27/0629
摘要： A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.
摘要翻译：正交肖特基二极管或具有肖特基二极管特性和MOS晶体管的器件串联耦合以提供泄漏电流和击穿电压的显着改进，只有正向电流的降低很小。在反向偏置情况下，存在小的反向偏置电流，但由于MOS晶体管，肖特基二极管两端的电压保持较小。几乎所有的反向偏置电压都跨越MOS晶体管，直到MOS晶体管故障。然而，该晶体管击穿不是最初的破坏性，因为肖特基二极管限制了电流。随着反向偏压持续增加，肖特基二极管开始吸收更多的电压。这增加了漏电流，但是在晶体管和肖特基二极管之间的击穿电压稍微相加。

43. 发明授权

US08188543B2 Electronic device including a conductive structure extending through a buried insulating layer 有权
标题翻译：电子器件包括延伸穿过掩埋绝缘层的导电结构
公开(公告)号：US08188543B2
公开(公告)日：2012-05-29
申请号：US11556576
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
IPC分类号： H01L27/01
CPC分类号： H01L27/105 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋绝缘层和覆盖掩埋绝缘层的半导体层，其中半导体层基本上是单晶的。电子器件还可以包括延伸穿过半导体层和掩埋绝缘层并邻接衬底的导电结构，以及位于导电结构与半导体层和埋入绝缘层中的每一个之间的绝缘衬垫。

44. 发明申请

US20080122025A1 ELECTRONIC DEVICE INCLUDING A CONDUCTIVE STRUCTURE EXTENDING THROUGH A BURIED INSULATING LAYER 有权
标题翻译：电子设备，包括通过绝缘绝缘层延伸的导电结构
公开(公告)号：US20080122025A1
公开(公告)日：2008-05-29
申请号：US11556576
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
IPC分类号： H01L27/00
CPC分类号： H01L27/105 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋绝缘层和覆盖掩埋绝缘层的半导体层，其中半导体层基本上是单晶的。电子器件还可以包括延伸穿过半导体层和掩埋绝缘层并邻接衬底的导电结构，以及位于导电结构与半导体层和埋入绝缘层中的每一个之间的绝缘衬垫。

45. 发明授权

US07820519B2 Process of forming an electronic device including a conductive structure extending through a buried insulating layer 有权
标题翻译：形成包括延伸穿过掩埋绝缘层的导电结构的电子器件的工艺
公开(公告)号：US07820519B2
公开(公告)日：2010-10-26
申请号：US11556544
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang , Van Wong
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang , Van Wong
IPC分类号： H01L21/331
CPC分类号： H01L21/84 , H01L21/823481 , H01L21/823878 , H01L27/0617 , H01L27/08 , H01L27/088 , H01L27/1203
摘要： A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.
摘要翻译：形成电子器件的工艺可以包括提供绝缘体上半导体衬底，其包括位于第一半导体层和衬底之间的衬底，第一半导体层和掩埋绝缘层。该工艺还可以包括在半导体层内形成场隔离区域，以及形成延伸穿过半导体层和掩埋绝缘层的开口以露出衬底。该方法还可以包括在开口内形成导电结构，其中导电结构邻接衬底。

46. 发明授权

US08963241B1 Integrated MOS power transistor with poly field plate extension for depletion assist 有权
标题翻译：集成MOS功率晶体管，具有多场扩展功能，用于耗尽辅助
公开(公告)号：US08963241B1
公开(公告)日：2015-02-24
申请号：US13460717
申请日：2012-04-30
申请人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
发明人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0653 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/402 , H01L29/4238 , H01L29/7835
摘要： A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate and a polysilicon field plate. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more polysilicon extension tabs extend from the field plate to at least above the edge of the first doped region. The polysilicon gate is cut to form a cut-out region for the end of each polysilicon extension tab extending toward the body substrate. The one or more polysilicon extension tabs force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.
摘要翻译：分离栅极功率晶体管包括掺杂衬底，衬底上的栅氧化层，以及形成多晶硅栅极和多晶硅场板的栅极氧化物层上的分裂多晶硅层。两个多晶硅部分被间隙隔开。场板电耦合到分离栅功率晶体管的源极。一个或多个多晶硅延伸片从场板延伸到至少在第一掺杂区的边缘上方。多晶硅栅极被切割以形成朝向主体衬底延伸的每个多晶硅延伸片的端部的切出区域。一个或多个多晶硅延伸片将场板下面的过渡区域的部分强制为深度耗尽，从而防止在该区域中形成空穴反转层。

47. 发明授权

US08969958B1 Integrated MOS power transistor with body extension region for poly field plate depletion assist 有权
标题翻译：集成MOS功率晶体管，具有用于多场板耗尽辅助的主体延伸区域
公开(公告)号：US08969958B1
公开(公告)日：2015-03-03
申请号：US13460603
申请日：2012-04-30
申请人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
发明人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0653 , H01L29/1095 , H01L29/401 , H01L29/4238 , H01L29/66659 , H01L29/7835
摘要： A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate positioned over a channel region and a first portion of a transition region and a polysilicon field plate positioned over a second portion of the transition region and a shallow trench isolation region. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more body extension regions, each having the same doping type as the body substrate, extend at least underneath the edge of the field plate adjacent to the gap. The body extension regions force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.
摘要翻译：分离栅功率晶体管包括掺杂衬底，衬底上的栅极氧化物层和栅极氧化物层上的分离多晶硅层，其形成位于沟道区域上的多晶硅栅极和过渡区域的第一部分以及多晶硅位于过渡区域的第二部分上的场板和浅沟槽隔离区域。两个多晶硅部分被间隙隔开。场板电耦合到分离栅功率晶体管的源极。每个具有与主体基板相同的掺杂类型的一个或多个本体延伸区域至少延伸到邻近间隙的场板的边缘的下方。体延伸区域迫使场板下方的过渡区域的部分深度耗尽，从而防止在该区域中形成空穴反转层。

48. 发明授权

US07851857B2 Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications 有权
标题翻译：双电流路径LDMOSFET，具有分级PBL，适用于超高压智能电源应用
公开(公告)号：US07851857B2
公开(公告)日：2010-12-14
申请号：US12182398
申请日：2008-07-30
申请人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L29/78 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41775 , H01L29/4238 , H01L29/66681
摘要： A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.
摘要翻译：提供了双电流路径LDMOSFET晶体管（40），其包括衬底（400），渐变埋层（401），其中形成有漏极区（416）的外延漂移区（404），第一阱区 406），其中形成源区（412），与源极区（412）相邻形成以限定第一沟道区（107）的栅极（420），以及包括埋置的RESURF层的电流布线结构 408）与形成在外延层（404）的预定上部区域中的第二阱区域（414）欧姆接触，以便被栅电极（420）完全覆盖，电流布线结构与第一阱区域（406）和漏极区域（416）之间的区域，以描绘与源极区域和通过外延层的分离的电流路径。

49. 发明申请

US20100025756A1 Dual Current Path LDMOSFET with Graded PBL for Ultra High Voltage Smart Power Applications 有权
标题翻译：双电流路径LDMOSFET，具有用于超高压智能电源应用的分级PBL
公开(公告)号：US20100025756A1
公开(公告)日：2010-02-04
申请号：US12182398
申请日：2008-07-30
申请人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41775 , H01L29/4238 , H01L29/66681
摘要： A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.
摘要翻译：提供了双电流路径LDMOSFET晶体管（40），其包括衬底（400），渐变埋层（401），其中形成有漏极区（416）的外延漂移区（404），第一阱区 406），其中形成源区（412），与源极区（412）相邻形成以限定第一沟道区（107）的栅极（420），以及包括埋置的RESURF层的电流布线结构 408）与形成在外延层（404）的预定上部区域中的第二阱区（414）欧姆接触，以便被栅电极（420）完全覆盖，电流布线结构与第一阱区域（406）和漏极区域（416）之间的区域，以描绘与源极区域和通过外延层的分离的电流路径。

50. 发明授权

US07550804B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US07550804B2
公开(公告)日：2009-06-23
申请号：US11390796
申请日：2006-03-27
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1083 , H01L29/7816
摘要： A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).
摘要翻译：半导体器件可以包括具有第一掺杂剂类型的半导体衬底。半导体衬底内的第一半导体区域可以具有多个第一和第二部分（44,45）。第一部分（44）可以具有第一厚度，并且第二部分（54）可以具有第二厚度。第一半导体区域可以具有第二掺杂剂类型。半导体衬底内的多个第二半导体区域（42）可以各自定位在第一半导体区域的第一部分（44）的相应一个的正下方并直接位于第一半导体区域的第一部分（44）的下方中的至少一个，并且横向地位于相应的一对第二半导体区域第一半导体区域的部分（54）。半导体衬底内的第三半导体区域（56）可具有第一掺杂剂类型。栅电极（64）可以在第一半导体区域的至少一部分和第三半导体区域（56）的至少一部分之上。

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