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41. 发明授权

US5200350A Floating-gate memory array with silicided buried bitlines 失效
标题翻译：具有硅化掩埋位线的浮栅存储器阵列
公开(公告)号：US5200350A
公开(公告)日：1993-04-06
申请号：US736337
申请日：1991-07-26
申请人： Manzur Gill , Howard L. Tigelaar
发明人： Manzur Gill , Howard L. Tigelaar
IPC分类号： H01L27/115
CPC分类号： H01L27/115
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。字线之间和位线之间的隔离是厚场氧化物区域。一个厚场氧化物条将每个接地导线/位线对分开。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。所得到的结构是可编程存储器单元的密集交叉点阵列。

42. 发明授权

US5187683A Method for programming EEPROM memory arrays 失效
标题翻译： EEPROM存储器阵列编程方法
公开(公告)号：US5187683A
公开(公告)日：1993-02-16
申请号：US576307
申请日：1990-08-31
申请人： Manzur Gill , Sung-Wei Lin , Sebastiano D'Arrigo
发明人： Manzur Gill , Sung-Wei Lin , Sebastiano D'Arrigo
IPC分类号： G11C17/00 , G11C16/02 , G11C16/08 , G11C16/10 , H01L21/8247 , H01L27/115
CPC分类号： G11C16/08 , G11C16/10
摘要： A method is described for programming a semiconductor array of EEPROM cells. A selected cell is connected, by definition, to a selected source-column line, a selected drain-column line and a selected wordline. Each deselected memory cell in the array is connected to a deselected source-column line, a deselected drain-column line and/or a deselected wordline. The method includes preselecting first, second, third, fourth and fifth programming voltages such that the second programming voltage is more positive than the first programming voltage and such that the third, fourth and fifth programming voltages are intermediate between the first and second programming voltages. The first programming voltage is applied at least to a selected column line and to each of the same-type deselected column lines. The third programming voltage is applied to the selected wordline and the fourth programming voltage is applied to each deselected wordline. After a pre-charge time interval, the fifth programming voltage is applied to each same-type deselected column line and, after an optional additional pre-charge time interval, the second programming voltage is applied to the selected wordline. After a program time interval, the third programming voltage is applied to the selected wordline and, after an optional discharge time interval, the first programming voltage is applied to each same-type deselected column line. Each deselected wordline is maintained at the fourth programming voltage for an additional discharge time interval. The third, fourth and fifth programming voltages may have the same value.
摘要翻译：描述了一种用于编程EEPROM单元的半导体阵列的方法。根据定义，所选择的单元格连接到所选择的源列行，所选的排列列线和所选择的字线。阵列中的每个取消选择的存储单元连接到未选择的源 - 列线，取消选择的漏 - 列线和/或未选择的字线。该方法包括预选第一，第二，第三，第四和第五编程电压，使得第二编程电压比第一编程电压更正，并且使得第三，第四和第五编程电压在第一和第二编程电压之间。至少将第一编程电压施加到所选择的列线和每个相同类型的未选择的列线。将第三编程电压施加到所选择的字线，并且将第四编程电压施加到每个取消选择的字线。在预充电时间间隔之后，将第五编程电压施加到每个相同类型的未选择的列线，并且在可选的附加预充电时间间隔之后，将第二编程电压施加到所选择的字线。在编程时间间隔之后，将第三编程电压施加到所选择的字线，并且在可选的放电时间间隔之后，将第一编程电压施加到每个相同类型的未选择的列线。每个取消选择的字线保持在第四个编程电压下一个额外的放电时间间隔。第三，第四和第五编程电压可以具有相同的值。

43. 发明授权

US5168335A Electrically programmable, electrically erasable memory array cell with field plate 失效
标题翻译：电可编程，电可擦除存储阵列单元与现场板
公开(公告)号：US5168335A
公开(公告)日：1992-12-01
申请号：US741975
申请日：1991-08-06
申请人： Iano D'Arrigo , Manzur Gill , Sung-Wei Lin
发明人： Iano D'Arrigo , Manzur Gill , Sung-Wei Lin
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective source regions (30a, 30b), a shared drain region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) that controls the conductance of a respective subchannel region (74a, 74b) and may be programmed through Fowler-Nordheim electron tunneling through a respective tunnel oxide window (40a, 40b) from a respective source region (30a, 30b). A field plate conductor (40a) controls the conductance of respective subchannel regions (70a, 70b) within each channel region (38a, 38b). A word line or control gate conductor (62) is insulatively disposed adjacent respective third, remaining channel subregions (53a, 53b) and further is disposed insulatively adjacent the floating gates (46a, 46b) to program or erase them.
摘要翻译：在半导体层（10）的表面上形成一对电可擦除的电可编程存储单元，并且包括各自的源极区（30a，30b），共用漏极区（28）和各个沟道区（38a，38b）。每个单元具有控制相应子通道区域（74a，74b）的电导的浮栅导体（46a，46b），并且可以通过Fowler-Nordheim电子隧穿通过相应的隧道氧化物窗（40a，40b）从相应的源区域（30a，30b）。场板导体（40a）控制每个通道区域（38a，38b）内各个子通道区域（70a，70b）的电导。字线或控制栅极导体（62）被绝对地设置在相邻的第三剩余通道子区域（53a，53b）附近，并且还与浮动栅极（46a，46b）绝缘地设置以编程或擦除它们。

44. 发明授权

US5162879A Diffusionless conductor/oxide semiconductor field effect transistor and methods for making and using the same 失效
标题翻译：无扩散导体/氧化物半导体场效应晶体管及其制造和使用方法
公开(公告)号：US5162879A
公开(公告)日：1992-11-10
申请号：US786651
申请日：1991-11-01
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/336 , H01L29/08 , H01L29/78
CPC分类号： H01L29/66643 , H01L29/0847 , H01L29/78 , H01L29/7831
摘要： A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44). Source conductor (36) and drain conductor (38) are disposed to create inversion regions, and a second conductivity type opposite said first conductivity type, in the underlying source inversion region (40) and drain inversion region (42) of semiconductor layer (12) upon application of voltage. The transistor has a gate (54) insulatively overlying the channel region (44) to control the conductivity thereof.
摘要翻译：无扩散场效应晶体管形成在第一导电类型的半导体层（12）的表面，并且包括源极导体（36），漏极导体（38）和沟道区（44）。源极导体（36）和漏极导体（38）被设置成在半导体层（12）的下面的源极反向区域（40）和漏极反转区域（42）中产生反向区域和与第一导电类型相反的第二导电类型）施加电压。晶体管具有绝缘地叠置在沟道区（44）上以控制其导电性的栅极（54）。

45. 发明授权

US5156991A Fabricating an electrically-erasable, electrically-programmable read-only memory having a tunnel window insulator and thick oxide isolation between wordlines 失效
标题翻译：制造具有隧道窗绝缘体和字线之间的厚氧化物隔离的电可擦除的电可编程只读存储器
公开(公告)号：US5156991A
公开(公告)日：1992-10-20
申请号：US648087
申请日：1991-01-31
申请人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
发明人： Manzur Gill , Sebastiano D'Arrigo , Sung-Wei Lin
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L29/7883 , Y10S438/981
摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.
摘要翻译：使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了易于制造和减小电池尺寸。位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。隧道窗口提供的编程和擦除靠近或高于源的通道侧。窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。在优选实施例中，字线之间的隔离也是厚氧化物，进一步提高了耦合比。可以选择位线和字线间距来获得最佳间距或宽高比。位线到基板电容最小化。

46. 发明授权

US5151760A Integrated circuit with improved capacitive coupling 失效
标题翻译：具有改进的电容耦合的集成电路
公开(公告)号：US5151760A
公开(公告)日：1992-09-29
申请号：US738004
申请日：1991-07-30
申请人： Manzur Gill , David J. McElroy
发明人： Manzur Gill , David J. McElroy
IPC分类号： H01L21/28 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/7883
摘要： According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and the second conductor (16) is capacitively coupled to third conductor (22).
摘要翻译：根据本发明，提供了具有改进的电容耦合的集成电路，并且包括第一导体（20），第二导体（16）和第三导体（22）。第二导体（22）和第三导体（16）彼此相邻设置，由绝缘体区域（60）分开。第一导体（20）接触第三导体（16）并延伸穿过第三导体（22）的一部分。第一和第三导体被绝缘体区域（54）隔开。施加到第一导体（20）和第二导体（16）的电压电容耦合到第三导体（22）。

47. 发明授权

US5103273A Nonvolatile memory array having cells with two tunnelling windows 失效
标题翻译：具有具有两个隧道窗口的单元的非易失性存储器阵列
公开(公告)号：US5103273A
公开(公告)日：1992-04-07
申请号：US589347
申请日：1990-09-28
申请人： Manzur Gill , Theodore D. Lindgren
发明人： Manzur Gill , Theodore D. Lindgren
IPC分类号： G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115
摘要： A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first, second and third sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned over and insulated from the floating gates of the cells for reading, programming and erasing the cells. The row lines, including control gates, are also positioned over and insulated from the third sub-channels. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.
摘要翻译：具有用于编程和擦除的分离区域的非易失性存储单元。电池在半导体本体的表面上以阵列形成，每个电池包括作为源 - 列线的一部分的源，并且包括作为漏 - 列线的一部分的漏极。每个单元在源极和漏极之间具有第一，第二和第三子通道。每个电池单元的第一子通道的电导率由场板控制，该场板是位于第一子通道上并与第一子通道绝缘的场板 - 列 - 列线的一部分。每个第二子通道的电导率由形成在第二子通道上并与第二子通道绝缘的浮动栅极控制。每个浮动栅极具有位于相邻源极列线上方的第一隧道窗口，并且具有位于相邻排列 - 列线上方的第二隧道窗口。包括控制栅极的行线位于单元的浮动栅极上并与其隔离，用于读取，编程和擦除单元。包括控制栅极的行线也位于第三子通道上并与第三子通道绝缘。场板导体仅允许通过第一隧道窗口对单元进行编程，并且仅通过第二隧道窗口擦除单元，反之亦然。

48. 发明授权

US4947222A Electrically programmable and erasable memory cells with field plate conductor defined drain regions 失效
标题翻译：电气可编程和可擦除存储单元，具有定义漏极区域的导体板导体
公开(公告)号：US4947222A
公开(公告)日：1990-08-07
申请号：US385846
申请日：1989-07-26
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a, 28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60 a, 60b) to control their conductance. A control gate conductor is insulatively disposed adjacent the control gate subchannel regions (62a, 62b) to control their conductance. In another embodiment, the floating gate conductor (100) is replaced with a pair of field plate conductors (42a, 42b) that control the conductance of respective subchannel regions (64a, 64b). The field plate conductors (42a, 42b) act to self-align a diffused drain region (46) that replaces the inversion region (102).
摘要翻译：第一和第二EEPROM单元具有在半导体层（12）中形成为与第一导电类型相反的第二导电类型并且彼此间隔开的第一和第二源极区（28a，28b）。场平板导体（100）被绝缘地邻近并限定反转区域（102），并且还在第一和第二源极区域（28a，28b）之间横向隔开。当对场板导体（100）施加预定电压时，反转区域（102）从第一导电类型转换为第二导电类型。第一和第二通道区域（48a，48b）被限定在各个源极区域（28a，28b）和反转区域（102）之间，并且各自包括浮动栅极和控制栅极子通道区域（60a，62a，62b，60b）。第一和第二浮栅导体（40a，40b）被绝缘地设置在相邻的浮栅子通道区域（60a，60b）附近，以控制它们的电导。控制栅极导体与控制栅极子通道区域（62a，62b）相邻地间隔地设置以控制它们的电导。在另一个实施例中，浮动栅极导体（100）由控制各个子通道区域（64a，64b）的电导的一对场板导体（42a，42b）代替。场板导体（42a，42b）用于使取代反转区域（102）的扩散漏极区域（46）自对准。

49. 发明授权

US06912146B2 Using an MOS select gate for a phase change memory 失效
标题翻译：使用MOS选择栅极进行相变存储器
公开(公告)号：US06912146B2
公开(公告)日：2005-06-28
申请号：US10318705
申请日：2002-12-13
申请人： Manzur Gill , Tyler Lowrey
发明人： Manzur Gill , Tyler Lowrey
IPC分类号： G11C11/34 , G11C16/02 , G11C17/00 , H01L27/115 , H01L47/00
CPC分类号： G11C13/0004 , G11C2013/0071 , G11C2213/79
摘要： An NMOS field effect transistor may be utilized to drive the memory cell of a phase change memory. As a result, the leakage current may be reduced dramatically.
摘要翻译： NMOS场效应晶体管可用于驱动相变存储器的存储单元。结果，泄漏电流可能显着降低。

50. 发明授权

US5570314A EEPROM devices with smaller cell size 失效
标题翻译：具有较小单元尺寸的EEPROM器件
公开(公告)号：US5570314A
公开(公告)日：1996-10-29
申请号：US365208
申请日：1994-12-28
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/8247 , G11C11/34
CPC分类号： H01L27/11521
摘要： An EEPROM and method for making the same, having precisely shaped field oxide regions and memory cells, to provide improved electrical operating characteristics and increased memory density. A layer of field oxide is grown over an n-type substrate having a p-well and the layer of field oxide is selectively etched to form rows of field oxide. Rows of tunnel oxide are formed between the rows of field oxide. A first layer of polysilicon, or poly-1, is formed over the wafer and a layer of ONO is formed over the poly-1. Using the same mask, the ONO, poly-1, field oxide, and tunnel oxide are stack etched. Bit lines are formed, followed by oxide spacers. A second layer of polysilicon, or poly-2 is formed and selectively etched to form word lines. The exposed ONO and poly-1 are etched using the same mask to form floating gate regions. Subsequent process steps provide word lines to metal dielectric, contacts, metal and passivation.
摘要翻译：一种EEPROM及其制造方法，具有精确成形的场氧化物区域和存储单元，以提供改进的电气操作特性和增加的存储器密度。在具有p阱的n型衬底上生长场氧化物层，并且选择性地蚀刻场氧化物层以形成行场氧化物。隧道氧化物行形成在场氧化物行之间。在晶片上形成第一层多晶硅或多晶硅，并在多晶硅上形成一层ONO。使用相同的掩模，将ONO，poly-1，场氧化物和隧道氧化物进行叠层蚀刻。形成位线，随后形成氧化物间隔物。形成第二层多晶硅或多晶硅，并选择性地蚀刻以形成字线。使用相同的掩模蚀刻暴露的ONO和poly-1以形成浮栅区域。随后的工艺步骤为金属电介质，触点，金属和钝化提供字线。

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