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41. 发明申请

US20060227553A1 Actuator, optical device having actuator, and actuator manufacturing method 有权
标题翻译：执行器，具有致动器的光学装置和致动器制造方法
公开(公告)号：US20060227553A1
公开(公告)日：2006-10-12
申请号：US11348788
申请日：2006-02-07
申请人： Tomoaki Nakamura , Makoto Inoguchi
发明人： Tomoaki Nakamura , Makoto Inoguchi
IPC分类号： F21S8/00
CPC分类号： G02B26/0841 , B81B3/0051 , B81B2201/033 , B81B2201/042
摘要： An actuator includes: a base section; an object having a body portion and a holding portion holding the body portion in a manner that the body portion is movable against the base section; a movable comb-tooth portion extending from the object side in a direction substantially perpendicular to a formation direction of the holding portion; and a fixed comb-tooth portion which extends from the base section in a direction substantially perpendicular to the formation direction of the holding portion and which is arranged at a position at which the fixed comb-tooth portion is engaged with but having a gap from the movable comb-tooth portion; the fixed comb-tooth portion being composed of a steady-voltage-receiving fixed comb tooth that steadily supplies a drive voltage and a variable-voltage-receiving fixed comb tooth that receives a controlled voltage.
摘要翻译：致动器包括：基部; 物体具有主体部分和保持部分，其保持主体部分，使得主体部分能够相对于基部移动; 从所述物体侧沿与所述保持部的形成方向大致垂直的方向延伸的可动梳齿部; 以及固定梳齿部，其从与所述保持部的形成方向大致正交的方向从所述基部延伸，并且所述固定梳齿部配置在所述固定梳齿部与所述固定梳齿部接合的位置，活动梳齿部分; 固定梳齿部分由稳定地提供驱动电压的稳压接收固定梳齿和接收受控电压的可变电压接收固定梳齿构成。

42. 发明授权

US06957434B2 Distributed computing system 失效
标题翻译：分布式计算系统
公开(公告)号：US06957434B2
公开(公告)日：2005-10-18
申请号：US10342272
申请日：2003-01-15
申请人： Masahiko Saito , Takanori Yokoyama , Masaru Shimada , Kunihiko Tsunedomi , Tomoaki Nakamura
发明人： Masahiko Saito , Takanori Yokoyama , Masaru Shimada , Kunihiko Tsunedomi , Tomoaki Nakamura
IPC分类号： G06F15/16 , G06F9/46 , G06F9/48 , G06F9/50 , G06F15/177 , H04L29/08
CPC分类号： G06F9/505 , G06F9/4862 , G06F9/5083 , G06F9/54 , G06F2209/5021 , H04L67/10
摘要： A distributed computing system having a plurality of computers different from each other in performance, load, and type, uniformly manages local priority schemes adapted in the respective computers by utilizing the concept of “urgency” or “time limit”. Each of the computers includes a priority level conversion procedure for performing a conversion between an urgency level and a priority level of processing in accordance with the performance and the load of the computer, and a priority level changing procedure for changing a priority level of a program, which executes the processing, in accordance with a priority level indicated by the priority level conversion procedure.
摘要翻译：具有在性能，负载和类型上彼此不同的多个计算机的分布式计算系统通过利用“紧急”或“时间限制”的概念统一管理在各个计算机中适应的本地优先级方案。每个计算机包括根据计算机的性能和负载执行紧急度和优先级处理之间的转换的优先级转换过程，以及用于改变程序的优先级的优先级改变过程，其根据由优先级转换过程指示的优先级执行处理。

43. 发明授权

US06216236B1 Processing unit for a computer and a computer system incorporating such a processing unit 失效
标题翻译：用于计算机的处理单元和包含这种处理单元的计算机系统
公开(公告)号：US06216236B1
公开(公告)日：2001-04-10
申请号：US09188903
申请日：1998-11-10
申请人： Takeshi Miyao , Manabu Araoka , Tomoaki Nakamura , Masayuki Tanji , Shigenori Kaneko , Koji Masui , Saburou Iijima , Nobuyasu Kanekawa , Shinichiro Kanekawa , Yoshiki Kobayashi , Hiroaki Fukumaru , Katsunori Tagiri
发明人： Takeshi Miyao , Manabu Araoka , Tomoaki Nakamura , Masayuki Tanji , Shigenori Kaneko , Koji Masui , Saburou Iijima , Nobuyasu Kanekawa , Shinichiro Kanekawa , Yoshiki Kobayashi , Hiroaki Fukumaru , Katsunori Tagiri
IPC分类号： G06F1134
CPC分类号： G06F11/187 , G06F11/1064 , G06F11/141 , G06F11/1604 , G06F11/1641 , G06F11/1666 , G06F11/1679 , G06F11/18 , G06F11/181 , G06F11/184 , G06F11/185 , G06F11/20 , G06F11/2007 , G06F11/2028 , G06F11/203 , G06F11/2035 , G06F11/2043 , G06F12/0833 , G11C29/74
摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
摘要翻译：计算机系统具有经由一个或多个系统总线（1-1,1-2）连接的多个处理单元（2-1,2-2,2-n）。每个处理单元（2-1,2-2,2-n）在公共支撑板（PL）上具有三个或更多个处理器（20-1,20-2,20-3），并由公共时钟单元 1000）。三个处理器（20-1,20-2,20-3）执行相同的操作，并且通过比较三个处理器（20-1,20-2,20-3）的操作来检测处理器（20-1,20-2,20-3）中的故障（20-1,20-2,20-3）。如果一个处理器（20-1,20-2,20-3）失败，则可以在处理单元的其他两个处理器（20-1,20-2,20-3）中继续操作（2-1,2 -2,2-n），至少暂时在更换整个处理单元（2-1,2-2,2-n）之前。此外，处理单元（2-1,2-2,2-n）可以在时钟单元（1000）内具有多个时钟（A，B），具有切换装置，使得处理器（20-1， 20-2,20-n）通常从主时钟（A）接收时钟脉冲，但是如果主时钟（A）发生故障，则从辅助时钟（B）接收脉冲。在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。另外，多个高速缓冲存储器（220,221）可以共同地连接到处理器（20-1,20-2,20-3），使得一个高速缓冲存储器（220,221）的故障允许处理单元（2-1 ，2

44. 发明授权

US5901281A Processing unit for a computer and a computer system incorporating such a processing unit 失效
标题翻译：用于计算机的处理单元和包含这种处理单元的计算机系统
公开(公告)号：US5901281A
公开(公告)日：1999-05-04
申请号：US434288
申请日：1995-05-03
申请人： Takeshi Miyao , Manabu Araoka , Tomoaki Nakamura , Masayuki Tanji , Shigenori Kaneko , Koji Masui , Saburou Iijima , Nobuyasu Kanekawa , Shinichiro Kanekawa , Yoshiki Kobayashi , Hiroaki Fukumaru , Katsunori Tagiri
发明人： Takeshi Miyao , Manabu Araoka , Tomoaki Nakamura , Masayuki Tanji , Shigenori Kaneko , Koji Masui , Saburou Iijima , Nobuyasu Kanekawa , Shinichiro Kanekawa , Yoshiki Kobayashi , Hiroaki Fukumaru , Katsunori Tagiri
IPC分类号： G06F11/00 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G11C29/00 , G06F11/34
CPC分类号： G06F11/187 , G06F11/1064 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/1679 , G06F11/181 , G06F11/184 , G06F11/2007 , G06F11/2028 , G06F11/203 , G06F11/2035 , G06F11/2043 , G06F12/0833 , G06F11/1641 , G06F11/18 , G06F11/185 , G06F11/20 , G11C29/74
摘要： A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.
摘要翻译：计算机系统具有经由一个或多个系统总线连接的多个处理单元。每个处理单元在公共支撑板（PL）上具有三个或更多个处理器，并由公共时钟单元控制。三个处理器执行相同的操作，并且通过比较三个处理器的操作来检测处理器中的故障。如果一个处理器发生故障，则在更换整个处理单元之前，至少暂时在处理单元的其他两个处理器中继续操作。此外，处理单元可以在时钟单元内具有多个时钟（A，B），具有切换装置，使得处理器通常从主时钟（A）接收时钟脉冲，但是从辅助时钟（B ）如果主时钟（A）失败。在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。此外，多个高速缓冲存储器可以共同地连接到处理器，使得一个高速缓冲存储器的故障允许处理单元使用另一高速缓冲存储器继续操作。可以通过直接比较来实现高速缓冲存储器的内容的一致性，并且还可以使用比较方法来使处理器的内部高速缓冲存储器中的数据与外部高速缓冲存储器中的数据不同。协议的一致性还可以确保不同处理器单元的高速缓存中的数据总是正确的。

45. 发明授权

US5680270A Floppy disk apparatus which adjusts gain conforming to operation of carriage 失效
标题翻译：调整符合运输操作的增益的软盘装置
公开(公告)号：US5680270A
公开(公告)日：1997-10-21
申请号：US616892
申请日：1996-03-18
申请人： Tomoaki Nakamura
发明人： Tomoaki Nakamura
IPC分类号： G11B21/10 , G11B5/596
CPC分类号： G11B5/59622
摘要： The invention provides a floppy disk apparatus which can perform, where a carriage motor which makes a non-linear operation such as a linear stepping motor is employed, suitable gain adjustment conforming to operation of a carriage. Upon setting of a correction gain, the position of a magnetic head on a floppy disk medium is fixed by a main control section, and in this condition, servo information is read out from the floppy disk medium. From the servo information read out by the magnetic head, a tracking error signal is produced by a tracking error production section. Based on the thus produced tracking error signal, an operation amount calculation section calculates an operation amount of the carriage for one rotation of the floppy disk medium. A correction gain setting section calculates a correction gain based on the operation amount calculated by the operation amount calculation section, and sets the thus calculated correction gain to an operation amount correction section.
摘要翻译：本发明提供了一种软盘设备，其可以执行使诸如线性步进电机之类的非线性操作的滑架电动机，其适合于支架的操作的增益调节。在设定校正增益时，通过主控制部分固定磁盘介质上的磁头的位置，在该状态下，从软盘介质读出伺服信息。根据由磁头读出的伺服信息，跟踪误差产生部产生跟踪误差信号。基于由此产生的跟踪误差信号，操作量计算部分计算软盘介质的一次旋转的滑架的操作量。校正增益设定部根据由运算量计算部计算出的运算量来计算校正增益，并将这样计算出的校正增益设定为运算量校正部。

46. 发明授权

US5630135A Multiple-execution method of multiple-version programs and computer system therefor 失效
标题翻译：多版本程序及其计算机系统的多重执行方法
公开(公告)号：US5630135A
公开(公告)日：1997-05-13
申请号：US253482
申请日：1994-06-03
申请人： Masayuki Orimo , Kinji Mori , Katsumi Kawano , Shigeki Hirasawa , Hiroshi Fujise , Hitoshi Suzuki , Tomoaki Nakamura
发明人： Masayuki Orimo , Kinji Mori , Katsumi Kawano , Shigeki Hirasawa , Hiroshi Fujise , Hitoshi Suzuki , Tomoaki Nakamura
IPC分类号： G06F11/00 , G06F13/00
CPC分类号： G06F11/1487 , G06F11/1633 , G06F11/1654
摘要： A method for executing programs in a distributed processing system includes executing in a plurality of first processors different programs which perform the same function. Messages, containing data representing execution result output from said different programs and attribute information indicating function to be performed by the different programs, are transmitted from the first processors to a network. A second processor then receives these messages and selects a message therefrom based on an analysis of the attribute information contained in all of the received messages. The second processor then executes an application program using the data contained in the selected message. Alternatively, the message-selecting step is made based on both the attribute information and data contained in the messages received in the second processor. Each of the messages from the first processors may include graphic image data which can be analyzed and shown on a display.
摘要翻译：一种用于在分布式处理系统中执行程序的方法包括在多个第一处理器中执行执行相同功能的不同程序。包含表示来自所述不同程序的执行结果输出的数据和指示由不同程序执行的功能的属性信息的消息从第一处理器发送到网络。然后，第二处理器基于对包含在所有接收到的消息中的属性信息的分析，接收这些消息并从中选择一个消息。然后，第二处理器使用包含在所选择的消息中的数据来执行应用程序。或者，基于在第二处理器中接收的消息中包含的属性信息和数据两者来进行消息选择步骤。来自第一处理器的每个消息可以包括可以在显示器上分析和显示的图形图像数据。

47. 发明授权

US5343009A Data processing device and plug-in package 失效
标题翻译：数据处理设备和插件包
公开(公告)号：US5343009A
公开(公告)日：1994-08-30
申请号：US808610
申请日：1991-12-17
申请人： Manabu Araoka , Yoshiaki Takahashi , Atsushi Shikama , Yoshihiro Miyazaki , Tomoaki Nakamura , Masayuki Sakata
发明人： Manabu Araoka , Yoshiaki Takahashi , Atsushi Shikama , Yoshihiro Miyazaki , Tomoaki Nakamura , Masayuki Sakata
IPC分类号： G06F3/00 , G06F1/18 , H01H9/20 , H05K7/14
CPC分类号： H01H9/20 , Y10S439/911 , Y10T307/97
摘要： In a data processing device, when exchanging a plug-in package with another without breaking off the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.
摘要翻译：在数据处理装置中，在不断开向数据处理装置供给的电力的情况下与另一方交换插件式包装时，封装拆卸杆配备有锁定片。杠杆不移动，因此包装因此不能被移除，直到锁定件被释放。响应于锁定件的释放操作，启动开关以断开封装的电源。在完全安装包装后，通过锁定件的作用打开包装的电源，从而防止在拆卸包装时的任何误操作。

48. 发明授权

US5317461A Magnetic disk apparatus having a circuit for detecting a position of servo information recorded on a target track 失效
标题翻译：具有用于检测记录在目标轨道上的伺服信息的位置的电路的磁盘装置
公开(公告)号：US5317461A
公开(公告)日：1994-05-31
申请号：US860015
申请日：1992-03-30
申请人： Terumitsu Okamoto , Tomoaki Nakamura
发明人： Terumitsu Okamoto , Tomoaki Nakamura
IPC分类号： G11B21/10 , G11B5/596 , G11B20/10
CPC分类号： G11B5/59611
摘要： A magnetic disk apparatus detects servo information on a magnetic disk which includes a plurality of concentric tracks which are provided with an alternate arrangement of data areas and servo areas. The apparatus includes a servo ID detecting circuit which generates a first detection signal when a servo area including an identification signal is detected and a data reproducing circuit which generates a second detection signal when read data pulses are detected on the signal reproduced from the magnetic disk. Sampling pulses are generated when the second detection signal indicates that the generation of read data pulses has terminated, while the first detection signal indicates the presence of the identification signal. The positional error of the magnetic head of the magnetic disk apparatus with respect to the target track of the magnetic disk is determined from the servo information of the signal reproduced from the magnetic disk in synchronism with the sampling pulses.
摘要翻译：磁盘装置检测包括多个同心轨道的磁盘上的伺服信息，所述多个同心磁道设置有数据区域和伺服区域的替代布置。该装置包括伺服ID检测电路，当检测到包括识别信号的伺服区域时产生第一检测信号，并且当在从磁盘再现的信号上检测到读数据脉冲时产生第二检测信号的数据再现电路。当第二检测信号指示读数据脉冲的产生已经终止时产生采样脉冲，而第一检测信号指示存在识别信号。根据与采样脉冲同步的从磁盘重放的信号的伺服信息，确定磁盘装置的磁头相对于磁盘的目标磁道的位置误差。

49. 发明授权

US08826748B2 Stress-detecting element, sensor module, and electronic apparatus 有权
标题翻译：应力检测元件，传感器模块和电子设备
公开(公告)号：US08826748B2
公开(公告)日：2014-09-09
申请号：US13480000
申请日：2012-05-24
申请人： Tomoaki Nakamura , Tsutomu Nishiwaki
发明人： Tomoaki Nakamura , Tsutomu Nishiwaki
IPC分类号： G01L1/00
CPC分类号： G01L1/16 , G01L1/26 , G01L5/228
摘要： A stress-detecting element includes a support body, a support film, a first piezoelectric element, first and second elastic parts. The support body has an opening part with first and second rectilinear sections extending parallel to each other. The support film blocks off the opening part. The first piezoelectric element straddles the first rectilinear section from an interior area to an exterior area of the opening part as seen in plan view. The first elastic part straddles the first rectilinear section from the interior area to the exterior area of the opening part. The second elastic part straddles the second rectilinear section from the interior area to the exterior area of the opening part. The first and second elastic parts respectively have first and second elastic end sections disposed in the interior area of the opening part and spaced apart from each other.
摘要翻译：应力检测元件包括支撑体，支撑膜，第一压电元件，第一和第二弹性部件。支撑体具有开口部分，第一和第二直线部分彼此平行延伸。支撑膜阻挡开口部分。如平面图所示，第一压电元件将第一直线段从内部区域跨越到开口部分的外部区域。第一弹性部分将第一直线部分从内部区域跨越到开口部分的外部区域。第二弹性部分将第二直线部分从内部区域跨越到开口部分的外部区域。第一和第二弹性部分分别具有设置在开口部分的内部区域中并且彼此间隔开的第一和第二弹性端部。

50. 发明授权

US08803405B2 Ultrasonic transducer, biological sensor, and method for manufacturing an ultrasonic transducer 有权
标题翻译：超声波换能器，生物传感器以及制造超声波换能器的方法
公开(公告)号：US08803405B2
公开(公告)日：2014-08-12
申请号：US13479937
申请日：2012-05-24
申请人： Tomoaki Nakamura , Hironori Suzuki
发明人： Tomoaki Nakamura , Hironori Suzuki
IPC分类号： H01L41/08
CPC分类号： H01L41/23 , A61B8/0891 , A61B8/4227 , A61B8/4455 , B06B1/0651 , G01N29/36 , H01L41/0973 , H01L41/22 , H01L41/312 , H03H3/02 , H03H3/04 , H03H2003/045 , Y10T29/42 , Y10T29/49005 , Y10T29/49126
摘要： An ultrasonic transducer includes a resin substrate, a support film and a piezoelectric element. The resin substrate has an opening. The support film blocks off the opening in the resin substrate. The piezoelectric element is disposed on the support film in a region that blocks off the opening in plan view from a thickness direction of the support film. The piezoelectric element includes a lamination of a lower electrode, a piezoelectric body, and an upper electrode.
摘要翻译：超声波换能器包括树脂基板，支撑膜和压电元件。树脂基板具有开口。支撑膜阻挡树脂基板中的开口。压电元件设置在支撑膜上的从支撑膜的厚度方向俯视的开口部的区域。压电元件包括下电极，压电体和上电极的叠层。

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