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1. 发明授权

US5343009A Data processing device and plug-in package 失效
标题翻译：数据处理设备和插件包
公开(公告)号：US5343009A
公开(公告)日：1994-08-30
申请号：US808610
申请日：1991-12-17
申请人： Manabu Araoka , Yoshiaki Takahashi , Atsushi Shikama , Yoshihiro Miyazaki , Tomoaki Nakamura , Masayuki Sakata
发明人： Manabu Araoka , Yoshiaki Takahashi , Atsushi Shikama , Yoshihiro Miyazaki , Tomoaki Nakamura , Masayuki Sakata
IPC分类号： G06F3/00 , G06F1/18 , H01H9/20 , H05K7/14
CPC分类号： H01H9/20 , Y10S439/911 , Y10T307/97
摘要： In a data processing device, when exchanging a plug-in package with another without breaking off the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.
摘要翻译：在数据处理装置中，在不断开向数据处理装置供给的电力的情况下与另一方交换插件式包装时，封装拆卸杆配备有锁定片。杠杆不移动，因此包装因此不能被移除，直到锁定件被释放。响应于锁定件的释放操作，启动开关以断开封装的电源。在完全安装包装后，通过锁定件的作用打开包装的电源，从而防止在拆卸包装时的任何误操作。

2. 发明授权

US5418404A Data processing device and plug-in package 失效
标题翻译：数据处理设备和插件包
公开(公告)号：US5418404A
公开(公告)日：1995-05-23
申请号：US260367
申请日：1994-06-14
申请人： Manabu Araoka , Yoshiaki Takahashi , Atsushi Shikama , Yoshihiro Miyazaki , Tomoaki Nakamura , Masayuki Sakata
发明人： Manabu Araoka , Yoshiaki Takahashi , Atsushi Shikama , Yoshihiro Miyazaki , Tomoaki Nakamura , Masayuki Sakata
IPC分类号： G06F3/00 , G06F1/18 , H01H9/20 , H05K7/14 , H01R13/707
CPC分类号： H01H9/20 , Y10S439/911 , Y10T307/97
摘要： In a data processing device, when exchanging a plug-in package with another without breaking the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.
摘要翻译：在数据处理装置中，在不断开供给数据处理装置的电源的情况下与另一方交换插件式封装，但是，拆装杆配备有锁定片。杠杆不移动，因此包装因此不能被移除，直到锁定件被释放。响应于锁定件的释放操作，启动开关以断开封装的电源。在完全安装包装后，通过锁定件的作用打开包装的电源，从而防止在拆卸包装时的任何误操作。

3. 发明授权

US5551007A Method for controlling multiple common memories and multiple common memory system 失效
标题翻译：用于控制多个公共存储器和多个公共存储器系统的方法
公开(公告)号：US5551007A
公开(公告)日：1996-08-27
申请号：US121449
申请日：1993-09-16
申请人： Yoshihiro Miyazaki , Yoshiaki Takahashi , Manabu Araoka , Soichi Takaya , Hiroaki Fukumaru
发明人： Yoshihiro Miyazaki , Yoshiaki Takahashi , Manabu Araoka , Soichi Takaya , Hiroaki Fukumaru
IPC分类号： G06F12/00 , G06F11/18 , G06F13/368 , G06F15/173 , G06F13/40
CPC分类号： G06F15/173 , G06F13/368
摘要： A multiple common memory system is provided in which at least three CPUs share at least two common memories each storing one and the same content. Each of the first and second CPUs contains a respective one of the two common memories, and each of the first and second CPUs has an arrangement to access the common memory therein at the time of requesting a read access to a common memory. Other CPUs in the system do not contain common memories, but do include arrangements to access the common memory of the first or second CPU at the time of requesting a read access to a common memory.
摘要翻译：提供了多个公共存储器系统，其中至少三个CPU共享至少两个公共存储器，每个公共存储器存储一个和相同的内容。第一和第二CPU中的每一个包含两个公共存储器中的相应一个，并且在请求对公共存储器的读取访问时，第一和第二CPU中的每一个具有访问公共存储器的布置。系统中的其他CPU不包含公共存储器，但是在请求对公共存储器的读取访问时，确实包括访问第一或第二CPU的公共存储器的布置。

4. 发明授权

US6032265A Fault-tolerant computer system 失效
标题翻译：容错计算机系统
公开(公告)号：US6032265A
公开(公告)日：2000-02-29
申请号：US682956
申请日：1996-07-18
申请人： Hiroshi Oguro , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Soichi Takaya , Masataka Hiramatsu , Nobuo Akeura
发明人： Hiroshi Oguro , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Soichi Takaya , Masataka Hiramatsu , Nobuo Akeura
IPC分类号： G06F11/00 , G06F11/16 , G06F11/20 , G06F11/30 , G06F13/00 , G06F15/16
CPC分类号： G06F11/2056 , G06F11/2017 , G06F11/2046 , G06F11/004 , G06F11/16 , G06F11/1604 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/20 , G06F11/2005 , G06F11/2089
摘要： A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.
摘要翻译：容错计算机系统在使用替代I / O块来继续处理时防止I / O故障到达CPU块，使用具有最少专用外设电路的常用通用处理器。双系统总线适配器不在快速操作的CPU部分提供，需要复杂的封装技术，而是在CPU和I / O总线适配器之间的低速接口中。这允许CPU和I / O总线适配器在实现容错计算机系统的同时由普通数据处理器，工作站或个人计算机共享。如果在CPU或I / O总线适配器中出现单触发硬件故障，故障组件与系统断开连接，系统将不间断地运行。

5. 发明授权

US5852728A Uninterruptible clock supply apparatus for fault tolerant computer system 失效
标题翻译：用于容错计算机系统的不间断时钟提供装置
公开(公告)号：US5852728A
公开(公告)日：1998-12-22
申请号：US585344
申请日：1996-01-11
申请人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
发明人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
IPC分类号： G06F1/04 , G06F11/16 , G06F11/18 , G06F11/20 , G06F1/06
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/1679 , G06F11/20
摘要： The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.
摘要翻译：本发明涉及双时钟源中的任何一个时钟源的时钟源切换，而不会影响双系统中的时钟输出，从而防止其中的处理器的故障。在本发明的容错计算机系统中，多个处理单元中的每一个包括时钟源，时钟选择器，时钟停止检测单元，时钟相位调整单元和相位一致检测/操作抑制/复位单元，由此在时钟故障的情况下，当从故障时钟源切换到正常时钟源时，时钟相位调整单元确保输出时钟信号的连续性。设置在时钟选择器的后续级中的时钟相位调整单元插入具有通过降低其环路滤波器的增益而获得的过阻抗响应特性的PLL电路。

6. 发明授权

US5737513A Method of and system for verifying operation concurrence in maintenance/replacement of twin CPUs 失效
标题翻译：验证双CPU的维护/更换操作同步的方法和系统
公开(公告)号：US5737513A
公开(公告)日：1998-04-07
申请号：US650662
申请日：1996-05-20
申请人： Koji Matsuda , Yoshihiro Miyazaki , Soichi Takaya , Kazuhiro Hyuga , Nobuo Akeura , Shinichiro Yamaguchi , Naoto Miyazaki , Satoru Kayukawa
发明人： Koji Matsuda , Yoshihiro Miyazaki , Soichi Takaya , Kazuhiro Hyuga , Nobuo Akeura , Shinichiro Yamaguchi , Naoto Miyazaki , Satoru Kayukawa
IPC分类号： G06F15/16 , G06F11/16 , G06F15/177 , G06F11/22
CPC分类号： G06F11/1633 , G06F11/1645
摘要： A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure which, without the method and the system, would occur due to the initial fault of the replacement CPU during a dual subsystem synchronous operation carried out thereafter by the computer can be prevented from entailing a system down on both the subsystems.
摘要翻译：一种在双CPU计算机中采用的双CPU计算机中维护/更换双CPU的操作兼容性的方法，其中在在线维护/更换工作期间可能错误地安装了具有初始故障的替换CPU及其系统，其中，由于在由计算机执行的双子系统同步操作期间由于替换CPU的初始故障而导致的方法和系统的故障可以被防止在两个子系统上引起系统故障。

7. 发明授权

US5029073A Method for fast establishing a co-processor to memory linkage by main processor 失效
标题翻译：通过主处理器快速建立协处理器到存储器连接的方法
公开(公告)号：US5029073A
公开(公告)日：1991-07-02
申请号：US836820
申请日：1986-03-06
申请人： Soichi Takaya , Yoshihiro Miyazaki
发明人： Soichi Takaya , Yoshihiro Miyazaki
IPC分类号： G06F15/16 , G06F9/38 , G06F13/16 , G06F13/38 , G06F15/167 , G06F15/177
CPC分类号： G06F9/3877 , G06F13/16 , G06F15/167
摘要： A co-processor control method intended to speed up data transfer linkage between the co-processor and memory when the co-processor is activated by the main processor, in such a way that the main processor issues an active control signal to the co-processor in the cycle of reading out an operand in the memory onto the data bus by being addressed by the main processor so that the operand on the data bus is directly delivered to the co-processor.
摘要翻译：一种协处理器控制方法，用于在协处理器由主处理器激活时，加速协处理器和存储器之间的数据传输联动，使得主处理器向协处理器发出主动控制信号在通过由主处理器寻址而将存储器中的操作数读出到数据总线的循环中，使得数据总线上的操作数被直接传送到协处理器。

8. 发明授权

US4764869A Method and apparatus for controlling interruption in the course of instruction execution in a processor 失效
标题翻译：用于控制处理器中的指令执行过程中的中断的方法和装置
公开(公告)号：US4764869A
公开(公告)日：1988-08-16
申请号：US900987
申请日：1986-08-27
申请人： Yoshihiro Miyazaki , Soichi Takaya , Masayuki Tanji , Atsuhiko Nishikawa , Shinichiro Yamaguchi
发明人： Yoshihiro Miyazaki , Soichi Takaya , Masayuki Tanji , Atsuhiko Nishikawa , Shinichiro Yamaguchi
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4812
摘要： Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. The program level is fixed in this interruption so that the interrupt request is processed as a normal interrupt request at an interruption destination, and the processing is resumed from the interrupted point at a second return instruction after the interrupt processing.
摘要翻译：用于控制处理器中断的方法和装置。当在执行指令的过程中检测到具有比当前程序级别更高的优先级的外部中断请求时，处理被中断，并且发出间歇中断。在该中断中程序电平被固定，使得在中断目的地处理中断请求作为正常的中断请求，并且在中断处理之后的第二个返回指令处理从中断点恢复。

9. 发明授权

US5345566A Method and apparatus for controlling dual bus system 失效
标题翻译：用于控制双总线系统的方法和装置
公开(公告)号：US5345566A
公开(公告)日：1994-09-06
申请号：US825063
申请日：1992-01-24
申请人： Masayuki Tanji , Yoshihiro Miyazaki , Hiroaki Fukumaru , Syoji Yamaguchi , Koji Masui , Hisao Ogawa
发明人： Masayuki Tanji , Yoshihiro Miyazaki , Hiroaki Fukumaru , Syoji Yamaguchi , Koji Masui , Hisao Ogawa
IPC分类号： G06F11/14 , G06F11/18 , G06F11/20 , G06F13/00 , G06F13/364 , G06F13/40 , G06F13/42
CPC分类号： G06F13/4022 , G06F13/364
摘要： A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.
摘要翻译：一种用于控制双总线系统的方法和装置，即使双总线系统的总线之一发生故障，也能够实现高速和连续的操作。该方法和装置具有双总线系统，连接到双总线系统的两个总线的多个电子电路和用于向多个电子电路之一提供总线使用允许信号的总线控制器，所选择的一个电子电路根据从多个电子电路发出的请求数据传送的总线占用请求信号。如果双总线系统的两个总线的总线占用请求信号来自一个选定的电子电路，并且仲裁器的输出一致，那么总线使用允许信号被提供给一个所选择的电子电路，以允许占用两条总线的双总线系统。在两条总线完成数据传输时，确定双总线系统的数据传输完成。在出现故障时可以立即确保持续运转，能够实现计算机系统的高速运转。

10. 发明授权

US5146569A System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension 失效
标题翻译：用于存储微程序的重新启动地址，确定有效性的系统，以及在删除暂停时使用有效的重新启动地址恢复执行的系统
公开(公告)号：US5146569A
公开(公告)日：1992-09-08
申请号：US674398
申请日：1991-03-25
申请人： Shinichiro Yamaguchi , Hidekazu Matsumoto , Tadaaki Bandoh , Hirokazu Hirayama , Morioka Takayuki , Soichi Takaya , Yukio Kawamoto , Jushi Ide , Yoshihiro Miyazaki
发明人： Shinichiro Yamaguchi , Hidekazu Matsumoto , Tadaaki Bandoh , Hirokazu Hirayama , Morioka Takayuki , Soichi Takaya , Yukio Kawamoto , Jushi Ide , Yoshihiro Miyazaki
IPC分类号： G06F11/14
CPC分类号： G06F11/141
摘要： Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.
摘要翻译：微程序控制数据处理装置中的指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后暂停原因清除过程执行保存的内部信息被恢复。根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。

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