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41. 发明授权

US09585550B2 Rectal expander 有权
标题翻译：直肠扩张器
公开(公告)号：US09585550B2
公开(公告)日：2017-03-07
申请号：US10561649
申请日：2004-06-24
申请人： Eric Abel , James R. Hewit , Alan P. Slade , Zhigang Wang
发明人： Eric Abel , James R. Hewit , Alan P. Slade , Zhigang Wang
IPC分类号： A61M29/00 , A61B1/32 , A61B1/31
CPC分类号： A61B1/32 , A61B1/31 , A61M29/00
摘要： There is disclosed medical apparatus of the type for use in surgery such as transanal endoscopic microsurgery, as well as methods of providing access to, inspecting and enabling surgery within a body passage. In one embodiment of the invention, medical apparatus in the form of a rectal expander (10) is disclosed, the expander (10) being adapted for location at least partly within a body passage such as the rectum (12) of a patient (14), the expander (10) having a leading end (18) and an access area in the form of an opening (20) for access from the expander (10) into the rectum (12), at least part of the opening (20) being spaced from the leading end (18), and the expander (10) being controllably movable between collapse and expansion positions, for expanding the rectum (12).
摘要翻译：公开了用于外科手术的类型的医疗装置，例如经肛门内窥镜显微外科手术，以及提供身体通道内的进入，检查和使手术的方法。在本发明的一个实施例中，公开了直肠扩张器（10）形式的医疗装置，所述扩张器（10）适于至少部分位于身体通道内，例如患者（14）的直肠（12）），所述膨胀器（10）具有前端（18）和开口（20）形式的进入区域，用于从所述膨胀器（10）进入直肠（12），所述开口（20）的至少一部分）与所述前端（18）间隔开，并且所述膨胀器（10）可控制地在塌缩和膨胀位置之间移动，用于扩张直肠（12）。

42. 发明授权

US08864645B2 Hearing implant 有权
标题翻译：听力植入
公开(公告)号：US08864645B2
公开(公告)日：2014-10-21
申请号：US11795137
申请日：2006-01-13
申请人： Eric William Abel , Zhigang Wang
发明人： Eric William Abel , Zhigang Wang
IPC分类号： H04R25/02
CPC分类号： H04R25/606 , A61F2002/183 , H04R17/02
摘要： The present invention concerns an actuator for an implantable hearing aid for implantation into the human middle ear. The actuator comprises a substantially elongate piezoelectric component (34, 36) having first and second operating end faces (41, 43), said end faces extending substantially at right angles to the longitudinal axis of the piezoelectric component. Also there is provided a frame component comprising at least one flextensional amplifier element (32), the flextensional amplifier element being integral with and connecting first and second frame end portions (42, 44), the first and second frame end portions also extending substantially at right angles to longitudinal axis of the piezoelectric component when fitted thereto, whereby the first and second end portions are in contact with the piezoelectric component end faces.
摘要翻译：本发明涉及用于植入人中耳的可植入助听器的致动器。致动器包括具有第一和第二操作端面（41,43）的基本上细长的压电元件（34,36），所述端面基本上与压电元件的纵向轴线成直角延伸。还提供了一种包括至少一个张力放大器元件（32）的框架部件，该屈曲放大器元件与第一和第二框架端部（42,44）成一体并且连接第一和第二框架端部（42,44），第一和第二框架端部也基本上延伸与压电部件的纵轴成直角，由此第一和第二端部与压电元件端面接触。

43. 发明授权

US08742175B2 Para—or meso-functionalized aromatic ketone compounds, preparation methods thereof, and photopolymerization initiators comprising the same 有权
标题翻译：对 - 或内消旋官能化芳族酮化合物，其制备方法和包含它们的光聚合引发剂
公开(公告)号：US08742175B2
公开(公告)日：2014-06-03
申请号：US13695600
申请日：2011-11-04
申请人： Yongbo Zhang , Yanchao Wang , Yapeng Wang , Huaihai Song , Zhigang Wang
发明人： Yongbo Zhang , Yanchao Wang , Yapeng Wang , Huaihai Song , Zhigang Wang
IPC分类号： C07C49/00 , C07C45/00 , C07C211/00 , C07C217/00 , C07C261/00
CPC分类号： C08F2/50 , C07C49/784 , C07C49/83 , C07C49/84 , C07C59/90 , C07C62/38 , C07C69/16 , C07C69/18 , C07C69/30 , C07C69/54 , C07C69/75 , C07C69/757 , C07C69/82 , C07C225/16 , C07C229/60 , C07C323/22 , C07C2601/14 , C07D207/404 , C07D209/48 , C07D251/30 , C07F7/1804 , C08F2/48
摘要： The present invention discloses novel aromatic ketone compounds with functional substitution groups at para- or meta positions which can be used as photo-initiators or effective components of photo-initiator mixtures for the photopolymerizations of ethylenically unsaturated systems. The preparation of these compounds is also disclosed.
摘要翻译：本发明公开了具有在对位或间位具有官能取代基的新型芳族酮化合物，其可用作光引发剂或光引发剂混合物的有效成分，用于烯属不饱和体系的光聚合。还公开了这些化合物的制备。

44. 发明授权

US07851306B2 Method for forming a flash memory device with straight word lines 有权
标题翻译：用于形成具有直线字线的闪速存储器件的方法
公开(公告)号：US07851306B2
公开(公告)日：2010-12-14
申请号：US12327641
申请日：2008-12-03
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

45. 发明申请

US20100296225A1 Tunable Capacitors 有权
标题翻译：可调电容器
公开(公告)号：US20100296225A1
公开(公告)日：2010-11-25
申请号：US12626562
申请日：2009-11-25
申请人： Patrick Smith , Zhigang Wang
发明人： Patrick Smith , Zhigang Wang
IPC分类号： H01G4/06 , H01G7/00
CPC分类号： H01L27/016 , G08B13/2437 , H01L27/0207 , H01L27/0808 , H01L28/60 , H01L28/88 , Y10T29/43 , Y10T29/435 , Y10T29/49002 , Y10T29/49016
摘要： The present invention relates to tunable capacitors, devices including tunable capacitors, and methods of making and using tunable capacitors and devices. One or more secondary tunable capacitors can be connected to a primary capacitor by printing a connector conducting layer or feature to obtain a desired net capacitance. Digitally printing the connector conducting layer allows the number of secondary capacitors connected into the circuit to be determined during the integrated circuit fabrication process, without the need for individual masks connecting the appropriate number of secondary capacitors. This provides an in-process or post-process trimming method to obtain the desired precision and accuracy for capacitors. Various sizes and combinations of secondary capacitors can be connected to obtain high precision capacitors and/or improved matching of capacitance values.
摘要翻译：本发明涉及可调电容器，包括可调电容器的器件，以及制造和使用可调电容器和器件的方法。可以通过印刷连接器导电层或特征来将一个或多个二次可调谐电容器连接到主电容器，以获得期望的净电容。数字印刷连接器导电层允许在集成电路制造过程中确定连接到电路中的次级电容器的数量，而不需要连接适当数量的次级电容器的单独的掩模。这提供了一种过程中或后处理修剪方法，以获得电容器所需的精度和精度。可以连接各种尺寸和二次电容器的组合以获得高精度电容器和/或改善电容值的匹配。

46. 发明申请

US20100295661A1 Random Delay Generation for Thin-Film Transistor Based Circuits 有权
标题翻译：基于薄膜晶体管的电路的随机延迟生成
公开(公告)号：US20100295661A1
公开(公告)日：2010-11-25
申请号：US12625435
申请日：2009-11-24
申请人： Vivek SUBRAMANIAN , Mingming Mao , Zhigang Wang
发明人： Vivek SUBRAMANIAN , Mingming Mao , Zhigang Wang
IPC分类号： H04B7/24 , H04B1/04 , H03K3/36 , H03B5/12
CPC分类号： H04B1/04 , G06K7/0008 , G06K7/10059 , G06K19/0723 , H01L22/20 , H01L2924/0002 , H03B5/1203 , H03K3/0315 , H03K3/033 , H03K3/355 , H03K5/13 , H03K5/133 , H04H20/16 , H01L2924/00
摘要： Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.
摘要翻译：被配置为产生随机延迟的电路和电路元件，单稳态振荡器，被配置为广播重复消息无线系统的电路，以及用于形成这种电路，装置和系统的方法。本发明有利地提供了在无线电子应用中特别是RFID应用中基于TFT技术的相对较低成本的延迟产生电路。这种新颖的，技术上简化的，低成本的基于TFT的延迟产生电路实现了新颖的无线电路，设备和系统以及用于生产这样的电路，设备和系统的方法。

47. 发明授权

US07758083B2 Wall bushing for air conditioner 失效
标题翻译：空调墙壁套管
公开(公告)号：US07758083B2
公开(公告)日：2010-07-20
申请号：US11911790
申请日：2006-04-13
申请人： Boyang Ni , Zhigang Wang , Deyong Fang
发明人： Boyang Ni , Zhigang Wang , Deyong Fang
IPC分类号： F16L3/00
CPC分类号： F24F1/025 , F16L5/00 , F24F2007/001 , Y10S285/901
摘要： A wall bushing for an air-conditioner comprises an external pipe and an internal pipe. The cross section of the external pipe is a “sports ground” shape, and an inner circular wall of the external pipe is tangential to an outer circular wall of the internal pipe. An end of the internal pipe is connected to an air outlet port of the air conditioner, and an end of the external pipe is connected to an air inlet port.
摘要翻译：用于空调的壁套管包括外管和内管。外管的横截面是“运动场”形状，外管的内圆壁与内管的外圆壁相切。内管的一端连接到空调的出风口，外管的一端与进气口连接。

48. 发明授权

US07697330B1 Non-volatile memory array having drain-side segmentation for an FPGA device 有权
标题翻译：具有用于FPGA器件的漏极侧分割的非易失性存储器阵列
公开(公告)号：US07697330B1
公开(公告)日：2010-04-13
申请号：US11961203
申请日：2007-12-20
申请人： Vidyahara Bellippady , Santosh Yachareni , Fethi Dhaoui , Zhigang Wang
发明人： Vidyahara Bellippady , Santosh Yachareni , Fethi Dhaoui , Zhigang Wang
IPC分类号： G11C16/00
CPC分类号： G11C16/0441
摘要： A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.
摘要翻译：用于FPGA的非易失性存储器阵列包括以行和列排列并分成多个行段的多个存储单元。每个段中的每个非易失性存储器晶体管的源极耦合到一个共同的源极线。列分段线与阵列的每个段相关联，并且被耦合到段中的每个非易失性存储器晶体管的漏极。段选择晶体管耦合在每个列分段线与其相关联的列线之间，并且高电压驱动晶体管耦合到每个列线。

49. 发明授权

US07283398B1 Method for minimizing false detection of states in flash memory devices 有权
标题翻译：用于最小化闪速存储器件中的状态的错误检测的方法
公开(公告)号：US07283398B1
公开(公告)日：2007-10-16
申请号：US10838962
申请日：2004-05-04
申请人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
发明人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/344 , G11C16/3445 , G11C16/3477
摘要： The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.
摘要翻译：本发明提供一种用于确定闪存设备中的程序和擦除状态的方法。具体地，本发明的一个实施例公开了一种用于使非易失性浮动栅极存储单元的阵列中的状态的错误检测最小化的方法。多个字线被布置成多行。多个位线被布置在多个列中。该方法通过确定与一列存储器单元相关联的所选位线开始。然后，该方法通过在一个负电压下偏置一组字线来继续。字线组电耦合到相关联的存储器单元。当执行验证操作时，将负电压施加到字线组限制了来自存储器单元列中的相关联存储器单元的泄漏电流贡献。

50. 发明申请

US20070130553A1 Analog layout module generator and method 有权
标题翻译：模拟布局模块发生器和方法
公开(公告)号：US20070130553A1
公开(公告)日：2007-06-07
申请号：US11295268
申请日：2005-12-06
申请人： Zhigang Wang , Elias Fallon , Regis Colwell
发明人： Zhigang Wang , Elias Fallon , Regis Colwell
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5063
摘要： In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.
摘要翻译：在集成电路设计中的设备布局的计算机实现方法中，选择具有多个单元的阵列并将其存储在计算机的存储器中。在计算机的显示器上显示电路的多个互连电路装置的示意图。所显示的示意图的一个或多个电路装置由用户选择。响应于每个电路装置的选择，计算机的处理装置用电路装置的相应布局实例填充计算机的存储器中的阵列的空单元，其中每个布局实例表示材料的物理布置），形成相应的所选择的电路装置。

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