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41. 发明申请

US20070052063A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070052063A1
公开(公告)日：2007-03-08
申请号：US11514143
申请日：2006-09-01
申请人： Takehiro Ueda
发明人： Takehiro Ueda
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electric fuse includes a wide interconnect and a narrow interconnect. The electric fuse has a juxtaposed region in which a plurality of straight line portions are juxtaposed with each other by folding the wide interconnect and the narrow interconnect has a narrower width than that of the wide interconnect, and, at the same time, is connected to the wide interconnect outside the juxtaposed region.
摘要翻译：电熔丝包括宽互连和窄互连。电熔丝具有并列区域，其中多个直线部分通过折叠宽互连而并置，并且窄互连具有比宽互连的窄的宽度，并且同时连接到在并置区域之外的宽互连。

42. 发明申请

US20060171229A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060171229A1
公开(公告)日：2006-08-03
申请号：US11333359
申请日：2006-01-18
申请人： Takehiro Ueda
发明人： Takehiro Ueda
IPC分类号： G11C17/18
CPC分类号： G11C17/165 , G11C17/18 , G11C29/02 , G11C29/027
摘要： A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The potential difference imparting circuit 20 is configured as having a transfer gate 22 (first transfer gate), a terminal 24 (first terminal) and a terminal 26, so as to give a predetermined potential difference between both ends of the fuse 10 when disconnection of the fuse 10 is judged. The potential difference reducing circuit 30 is configured as having a transfer gate 32 (second transfer gate), a terminal 34 (second terminal) and a terminal 36, and reduces the potential difference between both ends of the fuse 10 applied by the above-described potential difference imparting circuit 20.
摘要翻译：图1所示的保险丝外围电路。 2具有保险丝10，电位差赋予电路20，电位差降低电路30，端子40，存储电路50，传输门60和逻辑门70.电位差赋予电路20被配置为具有传输门22（第一传输门），端子24（第一端子）和端子26，以便在断开保险丝10断开时给出保险丝10两端之间的预定电位差。电位差降低电路30被配置为具有传输门32（第二传输门），端子34（第二端子）和端子36，并且通过上述方式减小了熔断器10的两端之间的电位差电位差赋予电路20。

43. 发明申请

US20060171228A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060171228A1
公开(公告)日：2006-08-03
申请号：US11329161
申请日：2006-01-11
申请人： Takehiro Ueda
发明人： Takehiro Ueda
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The logic gate 70 is connected to the input end of the transfer gate 60. The logic gate 70 serves as a transmission prevention circuit preventing a signal stored in the memory circuit 50 from being transmitted to the fuse 10, when the disconnection judgment takes place.
摘要翻译：图1所示的保险丝外围电路。 2具有熔丝10，电位差赋予电路20，电位差减小电路30，端子40，存储电路50，传输门60和逻辑门70。逻辑门70连接到传输门60的输入端。当进行断开判断时，逻辑门70用作防止存储在存储电路50中的信号被传输到保险丝10的传输防止电路。

44. 发明授权

US6143592A MOS semiconductor device and method of fabricating the same 失效
标题翻译： MOS半导体器件及其制造方法
公开(公告)号：US6143592A
公开(公告)日：2000-11-07
申请号：US365017
申请日：1999-08-02
申请人： Takehiro Ueda
发明人： Takehiro Ueda
IPC分类号： H01L29/78 , H01L21/3115 , H01L21/314 , H01L21/318 , H01L21/336 , H01L21/768 , H01L23/00 , H01L21/00 , H01L21/8238 , H01L21/84
CPC分类号： H01L21/31155 , H01L21/3145 , H01L21/76825 , H01L21/76826 , H01L23/564 , H01L29/6659 , H01L2924/0002
摘要： There is provided a semiconductor device including a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a gate insulating layer sandwiched between the gate electrode and the semiconductor substrate, an interlayer insulating layer formed over the gate electrode and the semiconductor substrate, and a hydroxyl (OH) group trapper formed in the interlayer insulating layer. For instance, the hydroxyl group trapper is constituted of a nitrogen containing oxide layer. The semiconductor device is capable of preventing moisture contained in the interlayer insulating layer from penetrating the gate insulating layer and source/drain regions formed in the semiconductor substrate, resulting in that the semiconductor device can be kept away from being degraded because of hot carriers, even if the gate insulating layer were formed thinner.
摘要翻译：提供了一种半导体器件，包括半导体衬底，形成在半导体衬底上的栅电极，夹在栅电极和半导体衬底之间的栅极绝缘层，形成在栅电极和半导体衬底上的层间绝缘层，以及羟基（OH）基捕获器形成在层间绝缘层中。例如，羟基捕获器由含氮氧化物层构成。半导体器件能够防止层间绝缘层中含有的水分渗透到形成在半导体衬底中的栅极绝缘层和源极/漏极区域，导致半导体器件能够远离由于热载流子而劣化，甚至如果栅极绝缘层形成得更薄。

45. 发明申请

US20110284951A1 Semiconductor device and method of manufacturing the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110284951A1
公开(公告)日：2011-11-24
申请号：US13067243
申请日：2011-05-18
申请人： Takehiro Ueda , Hiroshi Kawaguchi
发明人： Takehiro Ueda , Hiroshi Kawaguchi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/4236 , H01L29/4238 , H01L29/665 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion.
摘要翻译：半导体器件包括在衬底的元件形成区域中形成有沟槽的晶体管，形成在沟槽的侧面和底面上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，以便掩埋沟槽，形成在基板的表面上的在栅极经度方向的一侧上形成的源极区域和形成在栅极经度方向上的另一侧的漏极区域。这里，栅极形成为在沟槽外部的基板上露出，并且栅电极被设置为覆盖沟槽的两端的上部，并且形成至少一个凹部，该凹部具有深度到达中心部分的基板。

46. 发明授权

US08056503B2 Plasma procesor and plasma processing method 有权
标题翻译：等离子处理和等离子体处理方法
公开(公告)号：US08056503B2
公开(公告)日：2011-11-15
申请号：US10483251
申请日：2002-07-02
申请人： Akihiro Kikuchi , Satoshi Kayamori , Shinya Shima , Yuichiro Sakamoto , Kimihiro Higuchi , Kaoru Oohashi , Takehiro Ueda , Munehiro Shibuya , Tadashi Gondai
发明人： Akihiro Kikuchi , Satoshi Kayamori , Shinya Shima , Yuichiro Sakamoto , Kimihiro Higuchi , Kaoru Oohashi , Takehiro Ueda , Munehiro Shibuya , Tadashi Gondai
IPC分类号： C23C16/50 , C23C16/52 , C23F1/00 , H01L21/306 , C23C16/06 , C23C16/22
CPC分类号： H01J37/32724 , C23C16/45565 , C23C16/509 , C23C16/5096 , H01J37/32082 , H01J37/32174 , H01J37/3244 , H01J37/32532 , H01J37/32623 , H01J37/32642 , H01J37/32715 , H01J37/3411 , H01J2237/002 , H01J2237/0206 , H01J2237/334 , H01L21/67069
摘要： An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., −400 to −600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
摘要翻译：蚀刻室1包括聚焦环9，以围绕设置在下电极4上的半导体晶片W.等离子体处理器设置有电位控制DC电源33以控制该聚焦环9的电位，以及这样构成为向下电极4提供例如-400至-600V的DC电压以控制聚焦环9的电位。这种结构防止表面电弧沿着待处理基板的表面发展。

47. 发明申请

US20080145556A1 METHOD FOR MANUFACTURING SUBSTRATE MOUNTING TABLE 审中-公开
标题翻译：制造基板安装表的方法
公开(公告)号：US20080145556A1
公开(公告)日：2008-06-19
申请号：US11954826
申请日：2007-12-12
申请人： Nobuyuki NAGAYAMA , Takehiro Ueda , Yoshiyuki Kobayashi , Kaoru Oohashi
发明人： Nobuyuki NAGAYAMA , Takehiro Ueda , Yoshiyuki Kobayashi , Kaoru Oohashi
IPC分类号： B05D1/08
CPC分类号： C23C16/4581 , C23C4/01 , C23C4/02 , C23C16/4404 , C23C16/46 , C23C16/466
摘要： A method for manufacturing a substrate mounting table having a mounting surface for mounting a substrate thereon; a plurality of gas injection openings opened on the mounting surface to supply a gas toward the mounting surface; a gas supply channel for supplying a gas to the gas injection openings; and a thermally sprayed ceramic layer covering the mounting surface is provided. The method includes forming a removable film at least on inner wall portions of the gas supply channel facing the gas injection openings; forming the thermally sprayed ceramic layer on the mounting surface; and removing the film.
摘要翻译：一种用于制造具有用于在其上安装基板的安装表面的基板安装台的方法; 多个气体注入口，其在所述安装面上开口，向所述安装面供给气体; 用于向气体注入口供给气体的气体供给通道; 并且提供覆盖安装表面的热喷涂陶瓷层。该方法包括至少在面向气体注入开口的气体供应通道的内壁部分上形成可移除膜; 在所述安装表面上形成所述热喷涂陶瓷层; 并去除胶片。

48. 发明申请

US20080122027A1 SEMICONDUCTOR DEVICE AND METHOD OF CUTTING ELECTRICAL FUSE 有权
标题翻译：半导体器件及切割电熔丝的方法
公开(公告)号：US20080122027A1
公开(公告)日：2008-05-29
申请号：US11749241
申请日：2007-05-16
申请人： Takehiro Ueda
发明人： Takehiro Ueda
IPC分类号： H01L29/00 , H01L21/479
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.
摘要翻译：半导体器件包括半导体衬底和电熔丝，电熔丝包括第一导体和第二导体，第一导体包括第一切割目标区域和从第一导体分支并连接到第一导体并且包括第二切割目标区域的第二导体，半导体衬底，其中在切断电熔丝的状态下，第一导体在第一切割目标区域和第二切割目标区域之间朝向外部流动形成流出区域。

49. 发明申请

US20070278617A1 Semiconductor device and method for determining fuse state 有权
标题翻译：用于确定熔丝状态的半导体器件和方法
公开(公告)号：US20070278617A1
公开(公告)日：2007-12-06
申请号：US11806553
申请日：2007-06-01
申请人： Norio Okada , Takehiro Ueda
发明人： Norio Okada , Takehiro Ueda
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： G11C17/18 , H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, a fuse which comprises a conductive material and is formed on a semiconductor substrate, a contacting target conductor region which is placed around the fuse on the semiconductor substrate and formed so as to make electrical contact with the fuse through the conductive material constituting the fuse when a process for cutting the fuse is carried out, and a determination unit which detects whether or not the fuse is electrically disconnected, and detects whether or not the contacting target conductor region and the fuse are electrically connected, and determines that the fuse is in a cut state when electrical disconnection of said fuse is detected or electrical connection between said contacting target conductor region and said fuse is detected.
摘要翻译：半导体器件包括半导体衬底，包括导电材料并形成在半导体衬底上的熔丝，接触目标导体区域，其被布置在半导体衬底上的保险丝周围并且形成为与保险丝电接触当执行用于切割熔丝的处理时构成熔丝的导电材料，以及检测熔丝是否断电的判断单元，并检测接触目标导体区域和熔丝是否电连接，以及当检测到所述保险丝的断电或检测到所述接触目标导体区域和所述保险丝之间的电连接时，确定所述保险丝处于切断状态。

50. 发明授权

US07282751B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07282751B2
公开(公告)日：2007-10-16
申请号：US10900205
申请日：2004-07-28
申请人： Takehiro Ueda
发明人： Takehiro Ueda
IPC分类号： H01L27/10 , H01L29/00 , H01L23/58 , H01L23/48
CPC分类号： H01L23/5256 , H01L23/345 , H01L23/525 , H01L23/528 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
摘要翻译：保险丝的熔融部分被板包围，使得在电流供应下在熔断器的熔化部分产生的热可以被限制或积聚在熔断器的熔化部分附近。这使得可以促进保险丝熔断。熔断器的熔化部分是折叠形式，而不是在这里单个由直线形式组成的保险丝，更容易将电流供应中产生的保险丝中的热量集中到熔化部分中，而且在另外有助于保险丝熔断。

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