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41. 发明申请

US20130200942A1 SOI BIPOLAR JUNCTION TRANSISTOR WITH SUBSTRATE BIAS VOLTAGES 有权
公开(公告)号：US20130200942A1
公开(公告)日：2013-08-08
申请号：US13369261
申请日：2012-02-08
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： G05F3/02
CPC分类号： H01L29/66234 , H01L21/761 , H01L27/082 , H01L27/1203 , H01L29/73
摘要： A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.

42. 发明授权

US08441084B2 Horizontal polysilicon-germanium heterojunction bipolar transistor 有权
标题翻译：水平多晶硅 - 锗异质结双极晶体管
公开(公告)号：US08441084B2
公开(公告)日：2013-05-14
申请号：US13048342
申请日：2011-03-15
申请人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L29/66 , H01L29/04
CPC分类号： H01L29/737 , H01L29/0808 , H01L29/0821 , H01L29/66242 , H01L29/66265
摘要： A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
摘要翻译：水平异质结双极晶体管（HBT）包括具有第一导电类型的掺杂的掺杂单晶Ge作为具有约0.66eV的能带隙的基极，以及掺杂有第二导电类型的掺杂多晶硅作为宽间隙 - 发射体具有约1.12eV的能带隙。在一个实施例中，采用具有第二导电类型掺杂的掺杂多晶硅作为集电极。在其它实施例中，采用具有第二导电类型掺杂的单晶Ge作为集电极。在这样的实施例中，由于基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。在两个实施例中，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

43. 发明申请

US20120282596A1 Sensor for Biomolecules 有权
标题翻译：生物分子传感器
公开(公告)号：US20120282596A1
公开(公告)日：2012-11-08
申请号：US13552727
申请日：2012-07-19
申请人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
发明人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
IPC分类号： G01N27/26
CPC分类号： G01N33/54373 , B82Y10/00 , G01N27/3276 , G01N27/4145 , G01N33/543 , H01L29/785 , Y10S977/721 , Y10S977/92 , Y10S977/953
摘要： A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current.
摘要翻译：用于感测电解质中的生物分子的方法包括将包含硅翅片的传感器的栅极电介质表面暴露于电解质，其中所述栅极电介质表面包括电介质材料和被配置为与所述生物分子结合的抗体; 对浸在电解质中的电极施加栅极电压; 并测量在硅片中流动的漏极电流的变化; 以及基于漏极电流的变化确定存在于电解质中的生物分子的量。

44. 发明授权

US08288758B2 SOI SiGe-base lateral bipolar junction transistor 有权
标题翻译： SOI SiGe基极横向双极结晶体管
公开(公告)号：US08288758B2
公开(公告)日：2012-10-16
申请号：US12958647
申请日：2010-12-02
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L29/06 , H01L31/109 , H01L31/0328 , H01L31/117
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

45. 发明授权

US08278200B2 Metal-semiconductor intermixed regions 有权
标题翻译：金属半导体混合区域
公开(公告)号：US08278200B2
公开(公告)日：2012-10-02
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

46. 发明申请

US20120235143A1 VERTICAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR 有权
标题翻译：垂直多晶硅锗绝缘双极晶体管
公开(公告)号：US20120235143A1
公开(公告)日：2012-09-20
申请号：US13048366
申请日：2011-03-15
申请人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/737 , H01L21/76229 , H01L29/0649 , H01L29/0821 , H01L29/165 , H01L29/66242 , H01L29/7375
摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
摘要翻译：垂直异质结双极晶体管（HBT）包括具有掺杂第一导电类型的掺杂多晶硅作为具有约1.12eV的能带隙的宽间隙发射极，并且具有掺杂第二导电类型的掺杂单晶Ge作为基极具有约0.66eV的能量带隙。采用具有第一导电类型掺杂的掺杂单晶Ge作为集电体。因为基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。此外，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

47. 发明授权

US08106458B2 SOI CMOS circuits with substrate bias 有权
标题翻译： SOI CMOS电路具有衬底偏置
公开(公告)号：US08106458B2
公开(公告)日：2012-01-31
申请号：US12348391
申请日：2009-01-05
申请人： Jin Cai , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78648
摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.
摘要翻译：本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置）电路，其位于绝缘体上硅（SOI）衬底上。具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。例如，可以使用正衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负衬底偏置电压可以用于增加n-FET的阈值电压，但是减少p-FET的电流。此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

48. 发明申请

US20110292733A1 ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF 有权
标题翻译：电气可编程浮动通用门CMOS器件及其应用
公开(公告)号：US20110292733A1
公开(公告)日：2011-12-01
申请号：US12786956
申请日：2010-05-25
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： G11C16/04 , H01L27/088
CPC分类号： H01L27/11521 , G11C16/0441 , H01L29/66825 , H01L29/7881
摘要： A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed repeatedly. The programming, erasure, and/or reprogramming can be effected by injection of electrons and/or holes into the floating gate. The programmable CMOS device can be employed as a fuse or an antifuse, to program a floating gate of another device, and/or to function as a latch. The programmable CMOS device can be formed employing standard logic compatible processes, i.e., without employing any additional processing steps.
摘要翻译：可编程CMOS器件包括具有公共浮动栅极的PFET和NFET。根据配置，可重复编程，擦除和重新编程可编程CMOS器件。编程，擦除和/或重新编程可以通过将电子和/或空穴注入浮动栅极来实现。可编程CMOS器件可用作熔丝或反熔丝，以编程另一器件的浮置栅极和/或用作锁存器。可编程CMOS器件可以使用标准逻辑兼容工艺形成，即不需要任何额外的处理步骤。

49. 发明申请

US20090108355A1 SOI CMOS CIRCUITS WITH SUBSTRATE BIAS 有权
标题翻译：具有基极偏置的SOI CMOS电路
公开(公告)号：US20090108355A1
公开(公告)日：2009-04-30
申请号：US12348391
申请日：2009-01-05
申请人： Jin Cai , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L27/092
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78648
摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.
摘要翻译：本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置）电路，其位于绝缘体上硅（SOI）衬底上。具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。例如，可以使用正衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负衬底偏置电压可以用于增加n-FET的阈值电压，但是减少p-FET的电流。此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

50. 发明授权

US06882015B2 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 失效
公开(公告)号：US06882015B2
公开(公告)日：2005-04-19
申请号：US10660755
申请日：2003-09-12
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L21/02 , H01L27/08 , H01L29/76
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

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