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1. 发明授权

US08278200B2 Metal-semiconductor intermixed regions 有权
标题翻译：金属半导体混合区域
公开(公告)号：US08278200B2
公开(公告)日：2012-10-02
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

2. 发明申请

US20120190192A1 Metal-Semiconductor Intermixed Regions 有权
公开(公告)号：US20120190192A1
公开(公告)日：2012-07-26
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

3. 发明申请

US20120295439A1 Metal-Semiconductor Intermixed Regions 审中-公开
标题翻译：金属半导体混合区域
公开(公告)号：US20120295439A1
公开(公告)日：2012-11-22
申请号：US13564181
申请日：2012-08-01
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

4. 发明授权

US08456011B2 Method to control metal semiconductor micro-structure 有权
公开(公告)号：US08456011B2
公开(公告)日：2013-06-04
申请号：US13006664
申请日：2011-01-14
申请人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
发明人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
IPC分类号： H01L23/532
CPC分类号： H01L21/768 , H01L21/28518 , H01L23/485 , H01L29/456 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

5. 发明申请

US20120181697A1 METHOD TO CONTROL METAL SEMICONDUCTOR MICRO-STRUCTURE 有权
标题翻译：控制金属半导体微结构的方法
公开(公告)号：US20120181697A1
公开(公告)日：2012-07-19
申请号：US13006664
申请日：2011-01-14
申请人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
发明人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/768 , H01L21/28518 , H01L23/485 , H01L29/456 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.
摘要翻译：一种形成金属半导体合金的方法，其包括在半导体衬底的第一深度上形成混合金属半导体区域而没有热扩散。将混合后的金属半导体区域退火以形成织构化的金属半导体合金。在纹理金属半导体合金上形成第二金属层。纹理金属半导体合金上的第二金属层然后退火以形成金属半导体合金接触，其中来自第二金属层的金属元素通过织构化金属半导体合金扩散以提供模板化的金属半导体合金。模板化金属半导体合金的厚度范围为15nm〜50nm的金属半导体合金的晶粒尺寸大于2×。

6. 发明授权

US08349716B2 Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device 失效
标题翻译：具有减小的结漏电的半导体器件和形成这种半导体器件的相关方法
公开(公告)号：US08349716B2
公开(公告)日：2013-01-08
申请号：US12911186
申请日：2010-10-25
申请人： Ming Cai , Christian Lavoie , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Ming Cai , Christian Lavoie , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/336 , H01L21/04
CPC分类号： H01L21/2257 , H01L21/28512 , H01L21/28518 , H01L29/665 , H01L29/66643
摘要： Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.
摘要翻译：公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。具体地说，形成具有p-n结的半导体层。在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

7. 发明申请

US20120098042A1 SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE 失效
标题翻译：具有降低接合泄漏的半导体器件和形成这种半导体器件的相关方法
公开(公告)号：US20120098042A1
公开(公告)日：2012-04-26
申请号：US12911186
申请日：2010-10-25
申请人： Ming Cai , Christian Lavoie , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Ming Cai , Christian Lavoie , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L29/78 , H01L21/336 , H01L21/04
CPC分类号： H01L21/2257 , H01L21/28512 , H01L21/28518 , H01L29/665 , H01L29/66643
摘要： Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.
摘要翻译：公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。具体地说，形成具有p-n结的半导体层。在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

8. 发明授权

US08030154B1 Method for forming a protection layer over metal semiconductor contact and structure formed thereon 失效
标题翻译：用于在金属半导体接触和其上形成的结构上形成保护层的方法
公开(公告)号：US08030154B1
公开(公告)日：2011-10-04
申请号：US12849223
申请日：2010-08-03
申请人： Ahmet S. Ozcan , Christian Lavoie , Zhen Zhang , Bin Yang
发明人： Ahmet S. Ozcan , Christian Lavoie , Zhen Zhang , Bin Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper surface of the gate structure and on an exposed surface of the semiconductor substrate that is adjacent to the gate structure. An upper surface of the metal semiconductor alloy is converted to an oxygen-containing protective layer. The sidewall spacers are removed using an etch that is selective to the oxygen-containing protective layer. A strain-inducing layer is formed over the gate structure and the semiconductor surface, in which at least a portion of the strain-inducing layer is in direct contact with the sidewall surface of the gate structure. In another embodiment, the oxygen-containing protective layer of the metal semiconductor alloy is provided by a two stage annealing process.
摘要翻译：在一个实施例中，提供了一种形成半导体器件的方法，其包括在半导体衬底上提供栅极结构。侧壁间隔件可以与栅极结构相邻地形成。可以在栅极结构的上表面和与栅极结构相邻的半导体衬底的暴露表面上形成金属半导体合金。将金属半导体合金的上表面转化为含氧保护层。使用对含氧保护层具有选择性的蚀刻来去除侧壁间隔物。应变诱导层形成在栅极结构和半导体表面上，其中应变诱导层的至少一部分与栅极结构的侧壁表面直接接触。在另一个实施方案中，金属半导体合金的含氧保护层通过两阶段退火工艺提供。

9. 发明申请

US20120112292A1 INTERMIXED SILICIDE FOR REDUCTION OF EXTERNAL RESISTANCE IN INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：用于降低集成电路设备中外部电阻的硅酮
公开(公告)号：US20120112292A1
公开(公告)日：2012-05-10
申请号：US12940394
申请日：2010-11-05
申请人： CHRISTIAN LAVOIE , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： CHRISTIAN LAVOIE , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L27/118 , H01L21/44
CPC分类号： H01L29/7833 , H01L21/26566 , H01L21/28518 , H01L29/41775 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： A method for forming an alternate conductive path in semiconductor devices includes forming a silicided contact in a source/drain region adjacent to an extension diffusion region and removing sidewall spacers from a gate structure. A metal layer is formed over a portion of the extension diffusion region in a substrate layer to intermix metal from the metal layer with the portion of the extension region without annealing the metal layer. An unmixed portion of the metal layer is removed. The alternate conductive path is formed on the extension diffusion region with intermixed metal by thermal processing after the unmixed portion of the metal layer has been removed.
摘要翻译：在半导体器件中形成交替导电路径的方法包括在与延伸扩散区相邻的源极/漏极区域中形成硅化物接触，并从栅极结构去除侧壁间隔物。在衬底层中的延伸扩散区域的一部分上形成金属层，以将来自金属层的金属与延伸区域的部分混合，而不退火金属层。除去金属层的未混合部分。在去除了金属层的未混合部分之后，通过热处理在互补导电路径上形成具有混合金属的延伸扩散区域。

10. 发明授权

US08652963B2 MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture 有权
标题翻译：具有均匀薄的硅化物层的MOSFET集成电路及其制造方法
公开(公告)号：US08652963B2
公开(公告)日：2014-02-18
申请号：US13237732
申请日：2011-09-20
申请人： Bin Yang , Christian Lavoie , Emre Alptekin , Ahmet S. Ozcan , Cung D. Tran , Mark Raymond
发明人： Bin Yang , Christian Lavoie , Emre Alptekin , Ahmet S. Ozcan , Cung D. Tran , Mark Raymond
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/6659 , H01L29/7833
摘要： An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.
摘要翻译：提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

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