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41. 发明申请

US20110163385A1 ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME 有权
标题翻译：包括斜面电压调节材料层的不对称FET及其制造方法
公开(公告)号：US20110163385A1
公开(公告)日：2011-07-07
申请号：US12683602
申请日：2010-01-07
申请人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
发明人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
IPC分类号： H01L27/092 , H01L29/78 , H01L27/088 , H01L21/28
CPC分类号： H01L27/092 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/78
摘要： A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.
摘要翻译：提供一种半导体结构，其包括位于半导体结构的表面上的至少一个非对称栅极堆叠。所述至少一个非对称栅极堆叠包括从底部到顶部的高k栅极电介质，倾斜阈值电压调节材料层和栅极导体。还提供了一种形成这种半导体结构的方法，其中在形成相对于半导体结构的水平表面倾斜的沉积倾斜的阈值电压调节材料层中使用视线沉积工艺。

42. 发明申请

US20100289085A1 Asymmetric Semiconductor Devices and Method of Fabricating 失效
标题翻译：不对称半导体器件及其制造方法
公开(公告)号：US20100289085A1
公开(公告)日：2010-11-18
申请号：US12465818
申请日：2009-05-14
申请人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Haizhou Yin , Yue Liang , Xiaojun Yu
发明人： Jun Yuan , Dureseti Chidambarrao , Sunfei Fang , Haizhou Yin , Yue Liang , Xiaojun Yu
IPC分类号： H01L27/092 , H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/28132 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/6659 , H01L29/7835 , Y10S257/90
摘要： A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material.
摘要翻译：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的非对称栅极堆叠。非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。本发明的不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而本发明的不对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物由不同的导电材料构成，第二导电间隔物的基底直接接触阈值调节材料。

43. 发明授权

US07816219B2 Field effect transistors (FETs) with multiple and/or staircase silicide 有权
标题翻译：具有多个和/或阶梯硅化物的场效应晶体管（FET）
公开(公告)号：US07816219B2
公开(公告)日：2010-10-19
申请号：US11850076
申请日：2007-09-05
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.
摘要翻译：一种半导体结构及其形成方法。首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

44. 发明授权

US07785950B2 Dual stress memory technique method and related structure 有权
标题翻译：双应力记忆技术方法及相关结构
公开(公告)号：US07785950B2
公开(公告)日：2010-08-31
申请号：US11164114
申请日：2005-11-10
申请人： Sunfei Fang , Jun Jung Kim , Zhijiong Luo , Hung Y. Ng , Nivo Rovedo , Young Way Teh
发明人： Sunfei Fang , Jun Jung Kim , Zhijiong Luo , Hung Y. Ng , Nivo Rovedo , Young Way Teh
IPC分类号： H01L21/8238 , H01L21/469
CPC分类号： H01L21/823864 , H01L21/823807
摘要： A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.
摘要翻译：公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。

45. 发明授权

US07585773B2 Non-conformal stress liner for enhanced MOSFET performance 失效
标题翻译：非保形应力衬垫，用于增强MOSFET性能
公开(公告)号：US07585773B2
公开(公告)日：2009-09-08
申请号：US11556591
申请日：2006-11-03
申请人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
发明人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
IPC分类号： H01L29/72
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.
摘要翻译：提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。本发明是针对制造所述半导体器件的方法。

46. 发明授权

US07482215B2 Self-aligned dual segment liner and method of manufacturing the same 有权
标题翻译：自对准双段衬管及其制造方法
公开(公告)号：US07482215B2
公开(公告)日：2009-01-27
申请号：US11468536
申请日：2006-08-30
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L21/8238 , H01L21/302 , H01L21/461 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/823807 , H01L29/7843
摘要： A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.
摘要翻译：提供一种形成覆盖第一组和第二组半导体器件的双段衬套的方法。该方法包括在其顶部形成第一衬垫和第一保护层，第一衬套覆盖第一组半导体器件; 形成第二衬垫，所述第二衬套具有覆盖所述第一保护层的第一部分，过渡部分和覆盖所述第二组半导体器件的第二部分，所述第二部分经由所述过渡部分自对准到所述第一衬里; 在所述第二衬垫的所述第二部分的顶部上形成第二保护层; 移除所述第二衬套的所述第一部分和所述过渡部分的至少一部分; 并且获得包括第一衬套，第二衬套的过渡部分和第二部分的双段衬管。还提供了根据本发明的一个实施例形成的具有自对准双段衬垫的半导体结构。

47. 发明申请

US20090017586A1 CHANNEL STRESS MODIFICATION BY CAPPED METAL-SEMICONDUCTOR LAYER VOLUME CHANGE 审中-公开
标题翻译：通过金属半导体层的体积变化改变通道应力
公开(公告)号：US20090017586A1
公开(公告)日：2009-01-15
申请号：US11774841
申请日：2007-07-09
申请人： Sunfei Fang , Zhijiong Luo
发明人： Sunfei Fang , Zhijiong Luo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L29/49 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7845
摘要： A method for fabricating a field effect device, such as a field effect transistor, uses a first metal-semiconductor layer, such as a first metal-silicide layer, adjacent a channel in the field effect device. The first metal-semiconductor layer has a first volume. The first metal-semiconductor layer is capped with a capping layer and processed to form a second metal-semiconductor layer that has a second volume different than the first volume. Due to the presence of the capping layer, the difference in volume between the second volume and the first volume introduces a stress into the channel of the field effect device.
摘要翻译：诸如场效应晶体管的场效应器件的制造方法在场效应器件中使用与沟道相邻的第一金属硅化物层等第一金属半导体层。第一金属半导体层具有第一体积。第一金属半导体层用封盖层封盖并加工成形成具有不同于第一体积的第二体积的第二金属半导体层。由于存在覆盖层，第二体积和第一体积之间的体积差异将引起场效应装置的通道中的应力。

48. 发明申请

US20080179638A1 GAP FILL FOR UNDERLAPPED DUAL STRESS LINERS 审中-公开
标题翻译：用于下压双重应力衬里的GAP填料
公开(公告)号：US20080179638A1
公开(公告)日：2008-07-31
申请号：US11669287
申请日：2007-01-31
申请人： Thomas W. Dyer , Sunfei Fang
发明人： Thomas W. Dyer , Sunfei Fang
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823425 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A gap fill nitride is formed in an underlapping region between a first semiconductor area with a first stress liner and a second semiconductor area with a second stress liner without plugging other tightly spaced structures. This is achieved by filling the tightly spaced structures with middle-of-line dielectric material such as silicon oxide in both the first and the second semiconductor areas prior to the formation of the gap fill nitride. The combination of the first and second stress liners and the gap fill nitride provides a continuous mobile ion diffusion barrier across the entire surface of a CMOS semiconductor structure.
摘要翻译：在具有第一应力衬垫的第一半导体区域和具有第二应力衬垫的第二半导体区域之间的重叠区域中形成间隙填充氮化物，而不堵塞其他紧密间隔的结构。这是通过在形成间隙填充氮化物之前在第一和第二半导体区域中填充紧密间隔的结构与中间线介电材料（例如氧化硅）来实现的。第一和第二应力衬垫和间隙填充氮化物的组合在CMOS半导体结构的整个表面上提供了连续的移动离子扩散势垒。

49. 发明申请

US20080122003A1 NON-CONFORMAL STRESS LINER FOR ENHANCED MOSFET PERFORMANCE 失效
标题翻译：非稳定应力衬管，用于增强MOSFET性能
公开(公告)号：US20080122003A1
公开(公告)日：2008-05-29
申请号：US11556591
申请日：2006-11-03
申请人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
发明人： Sunfei Fang , Jun Jung Kim , Thomas Dyer
IPC分类号： H01L27/092 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.
摘要翻译：提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。本发明是针对制造所述半导体器件的方法。

50. 发明申请

US20070298572A1 FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE 有权
标题翻译：具有多个和/或多个硅化物的场效应晶体管（FET）
公开(公告)号：US20070298572A1
公开(公告)日：2007-12-27
申请号：US11850076
申请日：2007-09-05
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.
摘要翻译：一种半导体结构及其形成方法。首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

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