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41. 发明申请

US20050112799A1 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 失效
公开(公告)号：US20050112799A1
公开(公告)日：2005-05-26
申请号：US10988768
申请日：2004-11-15
申请人： Simon Chooi , Yakub Aliyu , Mei Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Zhou , John Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Ho , Yi Xu
IPC分类号： H01L21/44 , H01L21/50 , H01L21/60 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

42. 发明申请

US20050090039A1 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 有权
公开(公告)号：US20050090039A1
公开(公告)日：2005-04-28
申请号：US10988692
申请日：2004-11-15
申请人： Simon Chooi , Yakub Aliyu , Mei Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
IPC分类号： H01L21/44 , H01L21/50 , H01L21/60 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

43. 发明授权

US06465157B1 Dual layer pattern formation method for dual damascene interconnect 有权
标题翻译：双镶嵌互连的双层图案形成方法
公开(公告)号：US06465157B1
公开(公告)日：2002-10-15
申请号：US09494638
申请日：2000-01-31
申请人： Jianxun Li , Mei Sheng Zhou , Subhash Gupta , Ming hui Far
发明人： Jianxun Li , Mei Sheng Zhou , Subhash Gupta , Ming hui Far
IPC分类号： G03F700
CPC分类号： H01L21/76811
摘要： A new method of forming dual damascene interconnects has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. A first photoresist layer is deposited overlying the dielectric layer. The first photoresist layer is exposed, but not developed, to define patterns where via trenches are planned. A second photoresist layer is deposited overlying the first photoresist layer. The second photoresist layer is exposed to define patterns where interconnect trenches are planned. The second photoresist layer and the first photoresist layer are developed to complete the via trench pattern of the first photoresist layer and the interconnect trench pattern of the second photoresist layer. The dielectric layer is etched through where defined by the via trench pattern of the first photoresist layer. The dielectric layer is etch where defined by the interconnect pattern of the second photoresist layer, and the dual damascene interconnect of the integrated circuit device is completed.
摘要翻译：已经实现了形成双镶嵌互连的新方法。提供半导体衬底。提供覆盖在半导体衬底上的电介质层。沉积在介电层上的第一光致抗蚀剂层。第一光致抗蚀剂层被暴露但未显影，以限定通过沟槽被规划的图案。第二光致抗蚀剂层沉积在第一光致抗蚀剂层上。暴露第二光致抗蚀剂层以限定互连沟槽被计划的图案。显影第二光致抗蚀剂层和第一光致抗蚀剂层以完成第一光致抗蚀剂层的通孔沟槽图案和第二光致抗蚀剂层的互连沟槽图案。电介质层被蚀刻到由第一光致抗蚀剂层的通孔沟槽图案限定的位置。介电层是由第二光致抗蚀剂层的互连图案限定的蚀刻，并且完成集成电路器件的双镶嵌互连。

44. 发明授权

US06740580B1 Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier 失效
标题翻译：通过向铜扩散阻挡层添加铝层来形成铜互连的方法
公开(公告)号：US06740580B1
公开(公告)日：2004-05-25
申请号：US09389633
申请日：1999-09-03
申请人： Subhash Gupta , Chyi S. Chern , Mei Sheng Zhou
发明人： Subhash Gupta , Chyi S. Chern , Mei Sheng Zhou
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.
摘要翻译：描述形成铜互连的方法。该方法可以用于形成单镶嵌或双镶嵌互连。向常规阻挡层添加铝阻挡层产生对铜扩散的优异屏障。提供基底层。沉积在基底层上的电介质层。图案化的电介质层形成互连沟槽。可以沉积可选的钛粘合层。覆盖在沟槽的内表面上的铝阻挡层被沉积。包含例如钛和氮化钛的第二阻挡层沉积在铝阻挡层上。沉积铜层，覆盖第二阻挡层并填充互连沟槽。铜层，第二阻挡层和铝阻挡层被抛光到介电层的顶表面以限定铜互连，并且完成集成电路器件的制造。

45. 发明授权

US06656643B2 Method of extreme ultraviolet mask engineering 有权
公开(公告)号：US06656643B2
公开(公告)日：2003-12-02
申请号：US09785116
申请日：2001-02-20
申请人： Subhash Gupta , Mei Sheng Zhou
发明人： Subhash Gupta , Mei Sheng Zhou
IPC分类号： G03F900
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/54
摘要： An EUV photolithographic mask device and a method of fabricating the same. The EUV photolithographic mask comprises a multi-layer over an EUV masking substrate and a patterned light absorbing layer formed on the multi-layer. The method comprises the steps of forming a multi-layer on an EUV mask substrate, forming a light absorbing layer on the multi-layer, and etching an opening through the light absorbing layer to the multi-layer. The light absorbing layer includes a metal selected from the group comprising nickel, chromium, cobalt, and alloys thereof, and is preferably nickel.

46. 发明授权

US06274499B1 Method to avoid copper contamination during copper etching and CMP 有权
标题翻译：在铜蚀刻和CMP期间避免铜污染的方法
公开(公告)号：US06274499B1
公开(公告)日：2001-08-14
申请号：US09442493
申请日：1999-11-19
申请人： Subhash Gupta , Paul Kwok Keung Ho , Mei Sheng Zhou , Ramasamy Chockalingam
发明人： Subhash Gupta , Paul Kwok Keung Ho , Mei Sheng Zhou , Ramasamy Chockalingam
IPC分类号： H01L21302
CPC分类号： H01L21/76801 , H01L21/3212 , H01L21/32134 , H01L21/76807 , H01L21/76834
摘要： In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or post-etching and post-CMP cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is described. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via is patterned and filled with a metal layer and planarized. A copper layer is deposited overlying the planarized metal layer and dielectric cap layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching and cleaning. In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A dual damascene opening is formed through the dielectric cap layer and the dielectric layer. A copper layer is deposited overlying a barrier metal layer over the dielectric cap layer and filling the dual damascene opening. The copper layer is polished back to leave the copper layer only within the dual damascene opening where the dielectric cap layer prevents copper contamination of the dielectric layer during polishing and cleaning.
摘要翻译：根据本发明的目的，描述了通过形成用于隔离下面介电层的电介质盖，在蚀刻，CMP或后蚀刻和后CMP清洗中防止金属间电介质层的铜污染的新方法。在本发明的一个实施例中，提供覆盖在半导体衬底上的电介质层。介电覆盖层沉积在介电层上。通孔被图案化并填充有金属层并且被平坦化。沉积在平坦化的金属层和电介质盖层上的铜层。铜层被蚀刻以形成铜线，其中电介质盖层在蚀刻和清洁期间防止电介质层的铜污染。在本发明的另一个实施例中，提供覆盖半导体衬底的电介质层。介电覆盖层沉积在介电层上。通过电介质盖层和电介质层形成双镶嵌开口。将铜层沉积在电介质盖层上方的阻挡金属层上，并填充双镶嵌开口。将铜层抛光回来，仅在双镶嵌开口中留下铜层，其中介电盖层在抛光和清洁期间防止电介质层的铜污染。

47. 发明授权

US06251786B1 Method to create a copper dual damascene structure with less dishing and erosion 有权
标题翻译：创建铜双镶嵌结构的方法，具有较少的凹陷和侵蚀
公开(公告)号：US06251786B1
公开(公告)日：2001-06-26
申请号：US09390783
申请日：1999-09-07
申请人： Mei Sheng Zhou , Paul Kwok Keung Ho , Subhash Gupta
发明人： Mei Sheng Zhou , Paul Kwok Keung Ho , Subhash Gupta
IPC分类号： H01L2100
CPC分类号： H01L21/76834 , H01L21/3212 , H01L21/76807 , H01L21/7684 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.
摘要翻译：在电介质层中产生双镶嵌结构，该结构包含阻挡层，而覆盖层可以设置在电介质层上，也可以不设置在电介质层上，以进一步保护双镶嵌结构。双镶嵌结构中的铜的表面是凹进的，通过CMP或等离子体蚀刻沉积并平面化/部分去除薄膜，从而在双镶嵌结构的铜上方提供坚固的表面，防止该镶嵌结构的凹陷和侵蚀表面。

48. 发明授权

US06184138B2 Method to create a controllable and reproducible dual copper damascene structure 有权
标题翻译：创建可控和可重复的双铜镶嵌结构的方法
公开(公告)号：US06184138B2
公开(公告)日：2001-02-06
申请号：US09390782
申请日：1999-09-07
申请人： Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta
发明人： Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76874 , H01L21/76876 , H01L21/76877 , H01L21/76879
摘要： A new method is provided to construct a copper dual damascene structure. A layer of IMD is deposited over the surface of a substrate. A cap layer is deposited over this layer of IMD, the dual damascene structure is then patterned through the cap layer and into the layer of IMD. A barrier layer is blanket deposited, a copper seed layer is deposited over the barrier layer. The dual damascene structure is then filled with a spin-on material. The barrier layer and the copper seed layer are removed above the cap layer; the cap layer can be partially removed or can be left in place. The spin on material remains in place in the via and trench opening during the operation of removing the copper seed layer and the barrier layer from above the cap surface thereby protecting the inside surfaces of these openings. The spin-on material is next removed from the dual damascene structure and copper is deposited. The cap layer that is still present above the surface of the IMD protects the dielectric from being contaminated with copper solution during the deposition of the copper. The excess copper is removed using a touch-up CMP. The cap layer over the surface of the IMD can, after the copper has been deposited, be removed if this is so desired. As a final step in the process, a liner or oxidation/diffusion protection layer is deposited over the dual damascene structure and its surrounding area.
摘要翻译：提供了一种构建铜双镶嵌结构的新方法。一层IMD沉积在衬底的表面上。覆盖层沉积在IMD的该层上，然后将双镶嵌结构通过盖层图案化并进入IMD层。阻挡层被覆盖沉积，铜晶种层沉积在阻挡层上。然后用镶嵌材料填充双镶嵌结构。在盖层上除去阻挡层和铜籽晶层; 盖层可以被部分地去除或可以留在原处。在从盖表面上方去除铜种子层和阻挡层的操作期间，材料上的旋转保持在通孔和沟槽开口中的适当位置，从而保护这些开口的内表面。随后从双镶嵌结构中去除旋涂材料，并沉积铜。仍然存在于IMD表面之上的盖层保护铜在沉积期间不被铜溶液污染。使用上层CMP去除多余的铜。如果这样做是希望的话，在沉积铜之后，IMD表面上的盖层可以被去除。作为该方法的最后一步，衬垫或氧化/扩散保护层沉积在双镶嵌结构及其周围区域上。

49. 发明授权

US06380087B1 CMP process utilizing dummy plugs in damascene process 有权
标题翻译：在镶嵌工艺中使用假插头的CMP工艺
公开(公告)号：US06380087B1
公开(公告)日：2002-04-30
申请号：US09596901
申请日：2000-06-19
申请人： Subhash Gupta , Mei Sheng Zhou , Ramasamy Chockalingam
发明人： Subhash Gupta , Mei Sheng Zhou , Ramasamy Chockalingam
IPC分类号： H01L21302
CPC分类号： H01L24/02 , H01L21/7684 , H01L21/76877 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , Y10S438/926
摘要： A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.
摘要翻译：一种制造具有至少一个集成电路的半导体晶片的方法，所述方法包括以下步骤。提供了至少具有上介电层和下电介质层的半导体晶片结构。该半导体晶片结构具有焊盘区域和互连区域。具有第一宽度的至少一个有源互连通过电介质层形成在互连区域中。通过电介质层的一部分，在焊盘区域中形成多个具有第二宽度的相邻虚拟插头。对半导体晶片结构进行图案化和蚀刻，以形成通过上部电介质层的沟槽。沟槽围绕至少一个有源互连和虚拟插头中的每一个，由此相邻虚拟插头之间的上部电介质层被去除。金属化层沉积在下电介质层上，至少填充到剩余的上电介质层的上表面上的沟槽。金属化层被平坦化以去除在焊盘区域内形成连续接合焊盘的多余的金属化层，并且包括多个相邻的虚设插头，从而形成包括至少一个相应的有源互连的至少一个镶嵌结构。

50. 发明授权

US06225221B1 Method to deposit a copper seed layer for dual damascene interconnects 有权
标题翻译：沉积双层镶嵌铜层的方法
公开(公告)号：US06225221B1
公开(公告)日：2001-05-01
申请号：US09501966
申请日：2000-02-10
申请人： Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta , Chockalingam Ramasamy
发明人： Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta , Chockalingam Ramasamy
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76874 , H01L21/76876 , H01L2221/1089
摘要： A new method of depositing a copper seed layer in the manufacture of an integrated circuit device has been achieved. The copper seed layer is thin and conformal and well-suited for subsequent electroless plating of copper. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer comprising tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer, and the integrated circuit is completed.
摘要翻译：已经实现了在制造集成电路器件中沉积铜种子层的新方法。铜种子层薄且保形，非常适合随后的铜化学镀。提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。图案化的电介质层形成用于计划的双镶嵌互连的通孔和沟槽。包含钽，钛或钨的阻挡层沉积在电介质层上，以对通孔和沟槽进行排列。通过CuF2蒸汽与阻挡层的反应沉积覆盖阻挡层的铜籽晶层，并且集成电路完成。

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