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41. 发明申请

US20060228829A1 Method for fabricating a flip chip package 有权
标题翻译：制造倒装芯片封装的方法
公开(公告)号：US20060228829A1
公开(公告)日：2006-10-12
申请号：US11162328
申请日：2005-09-07
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L21/48 , H01L21/50 , H01L21/44
CPC分类号： H01L24/16 , H01L23/49894 , H01L24/81 , H01L24/97 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/136 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81136 , H01L2224/8114 , H01L2224/81193 , H01L2224/81801 , H01L2224/83192 , H01L2224/83193 , H01L2224/97 , H01L2924/00013 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/30107 , H01L2224/81 , H01L2924/00014 , H01L2924/00
摘要： A flip chip packaging method is disclosed. First, a substrate is provided, in which the substrate comprises a plurality of integrated circuit (IC) package substrate units therein and the surface of each IC package substrate unit comprises a plurality of connecting pads. Next, an insulating layer with patterns is formed on the substrate and the connecting pads and a plurality of openings by partially exposing the upper surface of the connecting pads. Next, a conductive material is disposed within each opening. Next, a plurality of chips is provided, in which a plurality of conductive bumps is formed over the bottom surface of the chip. Lastly, the chips are mounted over the surface of the IC package substrate unit and the substrate is separated into a plurality of flip chip package structures, in which the surface of each flip chip package structure includes at least one chip.
摘要翻译：公开了一种倒装芯片封装方法。首先，提供基板，其中基板在其中包括多个集成电路（IC）封装基板单元，并且每个IC封装基板单元的表面包括多个连接焊盘。接下来，通过部分地暴露连接焊盘的上表面，在衬底和连接焊盘和多个开口上形成具有图案的绝缘层。接下来，在每个开口内设置导电材料。接下来，提供多个芯片，其中在芯片的底表面上形成多个导电凸块。最后，将芯片安装在IC封装基板单元的表面上，并且将基板分离成多个倒装芯片封装结构，其中每个倒装芯片封装结构的表面包括至少一个芯片。

42. 发明授权

US07112524B2 Substrate for pre-soldering material and fabrication method thereof 有权
标题翻译：预焊材料用基板及其制造方法
公开(公告)号：US07112524B2
公开(公告)日：2006-09-26
申请号：US10769451
申请日：2004-01-29
申请人： Shih-Ping Hsu , Chu-Chin Hu
发明人： Shih-Ping Hsu , Chu-Chin Hu
IPC分类号： H01L21/44
CPC分类号： H01L24/81 , H01L24/11 , H01L2224/0401 , H01L2224/05568 , H01L2224/11334 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/1607 , H01L2224/16225 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/0002 , H01L2924/01006 , H01L2924/01012 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15787 , H01L2924/351 , H05K3/3473 , H05K3/3484 , H05K2203/054 , H01L2924/00 , H01L2224/05552
摘要： A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.
摘要翻译：提出了一种用于预焊材料的衬底和该衬底的制造方法。提供具有形成有多个导电焊盘的至少一个表面的衬底。在衬底的表面上形成绝缘层，使得每个导电焊盘的顶表面露出。接下来，在绝缘层和导电焊盘上依次形成导电膜和抗蚀剂层，其中在抗蚀剂层中形成多个开口以暴露导电膜上方的导电膜的一部分。然后，通过模板印刷或电镀工艺将预焊材料沉积在导电焊盘上。

43. 发明申请

US20060177968A1 Method for fabricating semiconductor packages with semiconductor chips 审中-公开
标题翻译：制造具有半导体芯片的半导体封装的方法
公开(公告)号：US20060177968A1
公开(公告)日：2006-08-10
申请号：US11200009
申请日：2005-08-10
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L23/02 , H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L24/19 , H01L23/16 , H01L23/3128 , H01L23/36 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/7965 , H01L2224/97 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043 , H01L2224/82
摘要： A method for fabricating semiconductor packages with semiconductor chips includes: providing a reel tape capable of being rolled up, the reel tape for accommodating at least one row of carriers; mounting at least one semiconductor chip in each of the carriers, wherein a plurality of electrode pads are provided on an upper surface of the semiconductor chip; and forming a dielectric layer and a circuit layer on each set of the carriers and the semiconductor chips, wherein the circuit layer is electrically connected to the electrode pads of the semiconductor chip, so as to package the semiconductor chip in each of the carriers to form a package. The above method can continuously fabricate packages, and prevent imprecise positional alignment on a large carrier panel, as well as avoid the necessity of fabricating conductive bumps on the semiconductor chip for electrical connection, such that the fabrication costs can be reduced.
摘要翻译：一种用于制造具有半导体芯片的半导体封装的方法，包括：提供能够卷起的卷带，用于容纳至少一行载体的卷带; 在每个所述载体中安装至少一个半导体芯片，其中在所述半导体芯片的上表面上设置多个电极焊盘; 以及在每组载体和半导体芯片上形成电介质层和电路层，其中电路层电连接到半导体芯片的电极焊盘，以将半导体芯片封装在每个载体中以形成一套。上述方法可以连续地制造封装，并且防止在大载体面板上的不精确的位置对准，并且避免在用于电连接的半导体芯片上制造导电凸块的必要性，从而可以降低制造成本。

44. 发明申请

US20060145328A1 Three dimensional package structure with semiconductor chip embedded in substrate and method for fabricating the same 审中-公开
标题翻译：具有嵌入基板的半导体芯片的三维封装结构及其制造方法
公开(公告)号：US20060145328A1
公开(公告)日：2006-07-06
申请号：US11270945
申请日：2005-11-10
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/20 , H01L2224/211 , H01L2224/24227 , H01L2224/2518 , H01L2224/73267 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/351 , H05K1/185 , H05K3/4602 , H05K2201/10674 , H01L2924/00
摘要： A three dimensional package structure with semiconductor chip embedded in substrate and a method for fabricating the same are proposed. A carrier with at least one cavity is mounted on a first insulating layer, and at least one semiconductor chip is mounted on the first insulating layer and received in the cavity of the carrier. A second insulating layer is formed on the carrier and the semiconductor chip. By performing a pressing process on both of the first insulating layer and the second insulating layer, a gap between the carrier and the semiconductor chip is filled. A circuit layer may be formed on the second insulating layer and is electrically connected to the semiconductor chip. Heat dissipating vias are formed in the first insulating layer and are connected to the semiconductor chip and a heat dissipating circuit so as to facilitate dissipation of heat generated from the semiconductor chip.
摘要翻译：提出了一种具有嵌入基板的半导体芯片的三维封装结构及其制造方法。具有至少一个空腔的载体安装在第一绝缘层上，并且至少一个半导体芯片安装在第一绝缘层上并被接收在载体的空腔中。在载体和半导体芯片上形成第二绝缘层。通过对第一绝缘层和第二绝缘层进行压制处理，填充载体和半导体芯片之间的间隙。电路层可以形成在第二绝缘层上并与半导体芯片电连接。散热通孔形成在第一绝缘层中并连接到半导体芯片和散热电路，以便于散发从半导体芯片产生的热量。

45. 发明申请

US20060131176A1 Multi-layer circuit board with fine pitches and fabricating method thereof 有权
公开(公告)号：US20060131176A1
公开(公告)日：2006-06-22
申请号：US11160413
申请日：2005-06-22
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： C25D5/02
CPC分类号： C25D5/022 , H05K3/0023 , H05K3/045 , H05K3/107 , H05K3/421 , H05K3/423 , H05K3/4602 , H05K3/465 , H05K2201/0195 , H05K2201/09563 , H05K2203/0723 , Y10T29/53174
摘要： A method for fabricating a multi-layer circuit board with fine pitch is provided. First, a plurality of contact pads is disposed on a core substrate. Next, a first dielectric layer, a second dielectric layer, and a third dielectric layer are formed on the core circuit board, in which a plurality of patterned openings are formed in the third dielectric layer and a plurality of vias is formed in the first and second dielectric layer, and the vias are located at the openings corresponding to the contact pads. Next, a conductive seed layer is disposed on the patterned openings and vias and a conductive layer is disposed on the conductive seed layer for forming circuit in each patterned opening and conductive via. Finally, removing the conductive layers and the conductive seed layer on the surface of third dielectric layer and forming a separation for each conductive circuit at each opening.

46. 发明申请

US20060051952A1 Method for fabricating conductive bump of circuit board 有权
标题翻译：电路板导电凸块的制造方法
公开(公告)号：US20060051952A1
公开(公告)日：2006-03-09
申请号：US11079389
申请日：2005-03-15
申请人： Shih-Ping Hsu , Sao-Hsia Tang , Ying-Tung Wang , Wen-Hung Hu , Chao-Wen Shih , Meng-Da Chou
发明人： Shih-Ping Hsu , Sao-Hsia Tang , Ying-Tung Wang , Wen-Hung Hu , Chao-Wen Shih , Meng-Da Chou
IPC分类号： H01L21/44
CPC分类号： H05K3/3473 , H01L21/4853 , H01L23/49816 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H05K3/242 , H05K3/4602 , H05K2201/0352 , H05K2201/09436 , H05K2201/096 , H05K2203/043 , H05K2203/054 , H05K2203/0574 , H05K2203/1476 , H05K2203/1572 , H05K2203/1581 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first surface and the second surface, and conductive structures are formed in the circuit board for electrically connecting the circuit structures. Also, an insulating layer having a plurality of openings penetrating therethrough is formed on the circuit board for exposing the conductive pad. Then, a conductive layer is formed on a surface of the insulating layer having the opening formed on the first surface of the circuit board. An electroplating process is performed via the conductive layer and the conductive structure, such that a conductive bump is formed on the conductive pad located on the second surface of the circuit board. Subsequently, a resist layer is formed on the second surface of the circuit board to cover the conductive bump, and another resist layer having openings penetrating therethrough is formed on the first surface of the circuit board to expose the conductive pad. Finally, a conductive bump is formed on the conductive pad located on the first surface of the circuit board by an electroplating process. By such arrangement, the conductive bumps are successively formed on the first surface and the second surface of the circuit board.
摘要翻译：提出了一种用于制造电路板的导电凸块的方法。首先，提供具有第一表面和相应的第二表面的电路板。在所述第一表面和所述第二表面中的每一个上形成具有多个导电焊盘的电路结构，并且在所述电路板中形成导电结构以电连接所述电路结构。此外，在电路板上形成具有贯穿其中的多个开口的绝缘层，用于暴露导电焊盘。然后，在具有形成在电路板的第一表面上的开口的绝缘层的表面上形成导电层。通过导电层和导电结构进行电镀处理，使得在位于电路板的第二表面上的导电焊盘上形成导电凸块。随后，在电路板的第二表面上形成抗蚀剂层以覆盖导电凸块，并且在电路板的第一表面上形成具有贯穿其中的开口的另一个抗蚀剂层，以露出导电焊盘。最后，通过电镀工艺在位于电路板的第一表面上的导电焊盘上形成导电凸块。通过这种布置，导电凸块依次形成在电路板的第一表面和第二表面上。

47. 发明申请

US20050070084A1 Substrate for pre-soldering material and fabrication method thereof 有权
标题翻译：预焊材料用基板及其制造方法
公开(公告)号：US20050070084A1
公开(公告)日：2005-03-31
申请号：US10769451
申请日：2004-01-29
申请人： Shih-Ping Hsu , Chu-Chin Hu
发明人： Shih-Ping Hsu , Chu-Chin Hu
IPC分类号： H01L21/44 , H01L21/60 , H05K3/34
CPC分类号： H01L24/81 , H01L24/11 , H01L2224/0401 , H01L2224/05568 , H01L2224/11334 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/1607 , H01L2224/16225 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/0002 , H01L2924/01006 , H01L2924/01012 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15787 , H01L2924/351 , H05K3/3473 , H05K3/3484 , H05K2203/054 , H01L2924/00 , H01L2224/05552
摘要： A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.
摘要翻译：提出了一种用于预焊材料的衬底和该衬底的制造方法。提供具有形成有多个导电焊盘的至少一个表面的衬底。在衬底的表面上形成绝缘层，使得每个导电焊盘的顶表面露出。接下来，在绝缘层和导电焊盘上依次形成导电膜和抗蚀剂层，其中在抗蚀剂层中形成多个开口以暴露导电膜上方的导电膜的一部分。然后，通过模板印刷或电镀工艺将预焊材料沉积在导电焊盘上。

48. 发明授权

US06853084B2 Substrate within a Ni/Au structure electroplated on electrical contact pads and method for fabricating the same 无效
标题翻译：在电接触焊盘上电镀的Ni / Au结构中的衬底及其制造方法
公开(公告)号：US06853084B2
公开(公告)日：2005-02-08
申请号：US10364431
申请日：2003-02-10
申请人： Shih-Ping Hsu , Chiang-Du Chen , Yen-Hung Liu
发明人： Shih-Ping Hsu , Chiang-Du Chen , Yen-Hung Liu
IPC分类号： H01L21/48 , H01L23/498 , H05K3/24 , H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/49811 , H01L21/4846 , H01L2924/0002 , H05K3/243 , H05K2203/0542 , H05K2203/0577 , H05K2203/1476 , H01L2924/00
摘要： The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads. It improves the electrical coupling between gold wires and the electrical contact pads of the substrate, prevents the electrical contact pads from oxidation, and insurances the electrical interconnection performance.
摘要翻译：本发明公开了在电接触焊盘上电镀的Ni / Au结构内的基板及其制造方法。该方法包括：提供具有电路布局图案的衬底并在衬底的表面上形成导电膜; 在所述导电膜表面上的开口内沉积第一光致抗蚀剂层，以将所述电路布局图案的一部分暴露为电接触焊盘; 去除未被所述第一光致抗蚀剂层覆盖的暴露的导电膜; 沉积第二光致抗蚀剂层，覆盖暴露在第一光致抗蚀剂层的开口中的导电膜; 覆盖电接触垫表面的电镀Ni / Au; 去除第一和第二光致抗蚀剂，以及由光致抗蚀剂覆盖的导电膜; 在开口内的衬底上沉积焊料掩模以暴露所述电接触焊盘。它改善了金线和基片的电接触焊盘之间的电耦合，防止了电接触垫的氧化，并保证了电气互连性能。

49. 发明授权

US08779300B2 Packaging substrate with conductive structure 有权
标题翻译：具有导电结构的封装基板
公开(公告)号：US08779300B2
公开(公告)日：2014-07-15
申请号：US13355311
申请日：2012-01-20
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H05K1/11 , H01L29/40 , H01L23/48 , H01L23/00 , H01L23/498
CPC分类号： H01L24/00 , H01L23/498 , H01L23/49811 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L2224/03462 , H01L2224/0401 , H01L2224/05571 , H01L2224/05573 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05616 , H01L2224/05618 , H01L2224/05639 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11825 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13021 , H01L2224/13022 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13171 , H01L2224/13562 , H01L2224/13565 , H01L2224/136 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/14 , H01L2924/351 , H05K1/0271 , H05K3/243 , H05K3/3452 , H05K3/3473 , H05K3/4007 , H05K2201/0341 , H05K2201/0367 , H05K2201/099 , H05K2203/054 , H01L2924/014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post.
摘要翻译：提供一种具有导电结构的封装基板，包括其表面上具有至少一个导电焊盘的基板主体，设置在导电焊盘上的应力缓冲金属层，应力缓冲金属层的厚度为1-20μm，防焊层设置在基板主体上并且在其中具有至少一个开口，用于相应地暴露应力缓冲金属层的顶表面的一部分，设置在应力缓冲金属层的表面的中心部分上的金属柱，以及焊料凸块覆盖金属柱的表面。

50. 发明授权

US08022513B2 Packaging substrate structure with electronic components embedded in a cavity of a metal block and method for fabricating the same 有权
标题翻译：具有嵌入在金属块的空腔中的电子部件的封装基板结构及其制造方法
公开(公告)号：US08022513B2
公开(公告)日：2011-09-20
申请号：US12230273
申请日：2008-08-27
申请人： Shih-Ping Hsu
发明人： Shih-Ping Hsu
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05569 , H01L2224/05571 , H01L2224/16225 , H01L2224/24227 , H01L2224/32225 , H01L2924/00014 , H01L2924/01033 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H05K1/114 , H05K1/185 , H05K3/06 , H05K3/28 , H05K2201/09563 , H05K2201/09845 , H05K2201/10674 , H01L2224/05599 , H01L2224/05099
摘要： A packaging substrate structure with electronic components embedded therein and a method for fabricating the same are disclosed. The packaging substrate structure comprises a core board with a wiring layer on the two opposite surfaces thereof; a first built-up structure disposed on at least one surface of the core board and having a cavity to expose the surface of the core board; an electronic component disposed in the cavity and having an active surface and an inactive surface, where the active surface has pluralities of electrode pads and the inactive surface faces the surface of the core board; and a solder mask disposed on the surfaces of the first built-up structure and the electronic component, where the solder mask has pluralities of first openings to expose the electrode pads of the electronic component. Accordingly, the packaging substrate disclosed by the present invention can efficiently enhance electrical performance and product reliability.
摘要翻译：公开了一种其中嵌有电子部件的封装衬底结构及其制造方法。封装基板结构包括在其两个相对表面上具有布线层的芯板; 第一组合结构，设置在所述芯板的至少一个表面上并具有用于暴露所述芯板的表面的空腔; 设置在所述空腔中并具有活性表面和非活性表面的电子部件，其中所述活性表面具有多个电极焊盘，并且所述非活性表面面向所述芯板的表面; 以及设置在第一组合结构和电子部件的表面上的焊料掩模，其中焊料掩模具有多个第一开口以暴露电子部件的电极焊盘。因此，本发明公开的封装基板能够有效地提高电气性能和产品的可靠性。

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