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41. 发明授权

US08658389B2 Antibody conjugates 有权
标题翻译：抗体缀合物
公开(公告)号：US08658389B2
公开(公告)日：2014-02-25
申请号：US12381638
申请日：2009-03-13
申请人： Christopher Bieniarz , Jennifer Wong , Mark Lefever , Jerome W. Kosmeder, II , Julia Ashworth-Sharpe , Casey A. Kernag
发明人： Christopher Bieniarz , Jennifer Wong , Mark Lefever , Jerome W. Kosmeder, II , Julia Ashworth-Sharpe , Casey A. Kernag
IPC分类号： G01N33/535 , G01N33/53 , G01N33/532 , G01N21/76
CPC分类号： G01N33/535 , A61K47/65 , A61K47/6815 , C07K16/42 , C07K16/44 , C07K2317/76 , C12N9/0065 , C12N9/16 , C12N9/96
摘要： Antibody/signal-generating moiety conjugates are disclosed that include an antibody covalently linked to a signal-generating moiety through a heterobifunctional polyalkyleneglycol linker. The disclosed conjugates show exceptional signal-generation in immunohistochemical and in situ hybridization assays on tissue sections and cytology samples. In one embodiment, enzyme-metallographic detection of nucleic acid sequences with hapten-labeled probes can be accomplished using the disclosed conjugates as a primary antibody without amplification.
摘要翻译：公开了抗体/信号产生部分缀合物，其包括通过异双功能聚亚烷基二醇连接体与产生信号的部分共价连接的抗体。所公开的缀合物在组织切片和细胞学样品的免疫组织化学和原位杂交测定中显示出异常的信号产生。在一个实施方案中，用半抗原标记的探针对核酸序列的酶 - 金相检测可以使用所公开的缀合物作为一级抗体而无需扩增来完成。

42. 发明申请

US20090297576A1 Local Delivery of PAR-1 Antagonists to Treat Vascular Complications 审中-公开
标题翻译： PAR-1拮抗剂治疗血管并发症的局部输送
公开(公告)号：US20090297576A1
公开(公告)日：2009-12-03
申请号：US12131606
申请日：2008-06-02
申请人： Ayala Hezi-Yamit , Jennifer Wong
发明人： Ayala Hezi-Yamit , Jennifer Wong
IPC分类号： A61K9/00 , A61K31/443 , A61K31/56 , A61K33/00 , A61K31/662 , A61K39/395 , A61K31/7052 , A61K31/4353 , A61P9/00
CPC分类号： A61K9/1647 , A61K9/0024 , A61K31/4353 , A61K31/443 , A61K31/56 , A61K31/662 , A61K31/7052 , A61K45/06 , A61L31/10 , A61L31/16 , A61L2300/432 , A61L2300/45 , A61L2300/606 , A61K2300/00
摘要： Described herein are methods and medical devices used to deliver bioactive agents locally to patients in need of treatment and/or prevention of cardiovascular conditions Local delivery of protease-activated receptor 1 (PAR-1) antagonists are described herein from implantable medical devices including, but not limited to, stents.
摘要翻译：本文描述了用于将生物活性剂局部递送给需要治疗和/或预防心血管疾病的患者的方法和医疗装置。本文从可植入医疗装置中描述了蛋白酶活化受体1（PAR-1）拮抗剂的局部递送，包括但不限于不限于支架。

43. 发明授权

US07567997B2 Applications of cascading DSP slices 有权
标题翻译：级联DSP片的应用
公开(公告)号：US07567997B2
公开(公告)日：2009-07-28
申请号：US11019518
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/48
CPC分类号： G06F7/5443
摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
摘要翻译：在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。该IC允许实现一些基本的数学函数，例如加，减，乘和除。可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

44. 发明申请

US20090176253A1 Antibody conjugates 有权
标题翻译：抗体缀合物
公开(公告)号：US20090176253A1
公开(公告)日：2009-07-09
申请号：US12381638
申请日：2009-03-13
申请人： Christopher Bieniarz , Jennifer Wong , Mark Lefever , Jerome W. Kosmeder , Julia Ashworth-Sharpe , Casey A. Kernag
发明人： Christopher Bieniarz , Jennifer Wong , Mark Lefever , Jerome W. Kosmeder , Julia Ashworth-Sharpe , Casey A. Kernag
IPC分类号： G01N33/542 , G01N33/53
CPC分类号： G01N33/535 , A61K47/65 , A61K47/6815 , C07K16/42 , C07K16/44 , C07K2317/76 , C12N9/0065 , C12N9/16 , C12N9/96
摘要： Antibody/signal-generating moiety conjugates are disclosed that include an antibody covalently linked to a signal-generating moiety through a heterobifunctional polyalkyleneglycol linker. The disclosed conjugates show exceptional signal-generation in immunohistochemical and in situ hybridization assays on tissue sections and cytology samples. In one embodiment, enzyme-metallographic detection of nucleic acid sequences with hapten-labeled probes can be accomplished using the disclosed conjugates as a primary antibody without amplification.
摘要翻译：公开了抗体/信号产生部分缀合物，其包括通过异双功能聚亚烷基二醇连接体与产生信号的部分共价连接的抗体。所公开的缀合物在组织切片和细胞学样品的免疫组织化学和原位杂交测定中显示出异常的信号产生。在一个实施方案中，用半抗原标记的探针对核酸序列的酶 - 金相检测可以使用所公开的缀合物作为一级抗体而无需扩增来完成。

45. 发明申请

US20080058674A1 Tissue extraction device and method of using the same 审中-公开
标题翻译：组织提取装置及其使用方法
公开(公告)号：US20080058674A1
公开(公告)日：2008-03-06
申请号：US11511531
申请日：2006-08-29
申请人： Lex Jansen , Art Ferdinand , Hugues F. Malandain , Claudia Orellana , Chris Phan , Derek Rothwell , Jennifer Wong
发明人： Lex Jansen , Art Ferdinand , Hugues F. Malandain , Claudia Orellana , Chris Phan , Derek Rothwell , Jennifer Wong
IPC分类号： A61B10/00
CPC分类号： A61B10/0266 , A61B10/025 , A61B10/04 , A61B2017/00867
摘要： Apparatuses and methods for performing minimally invasive medical procedures are disclosed herein. In one example, an apparatus includes an elongate body that has a deformable distal portion and defines a lumen, the lumen extends through the deformable distal portion. The deformable distal portion has a cutting portion and defines an opening. The elongate body has a first configuration in which the opening is a first size and a second configuration in which the opening is a second size smaller than the first size of the opening. The elongate body in the first configuration is configured to be percutaneously inserted at least partially into a tissue such that at least a portion of the tissue is disposed within the lumen. The elongate body is configured to move to the second configuration when the elongate body reaches a threshold temperature while inserted in the tissue.
摘要翻译：本文公开了用于执行微创医疗程序的装置和方法。在一个示例中，设备包括具有可变形的远侧部分并限定内腔的细长主体，内腔延伸穿过可变形远端部分。可变形远端部分具有切割部分并限定开口。细长体具有第一构造，其中开口是第一尺寸和第二构造，其中开口是小于开口的第一尺寸的第二尺寸。第一构造中的细长体构造成至少部分地经皮地插入到组织中，使得组织的至少一部分设置在内腔内。细长体构造成当细长体在插入组织中时达到阈值温度时移动到第二构型。

46. 发明授权

US07216277B1 Self-repairing redundancy for memory blocks in programmable logic devices 有权
标题翻译：可编程逻辑器件中的存储器块的自修复冗余
公开(公告)号：US07216277B1
公开(公告)日：2007-05-08
申请号：US10717040
申请日：2003-11-18
申请人： Tony K. Ngai , Jennifer Wong , Wayson J. Lowe
发明人： Tony K. Ngai , Jennifer Wong , Wayson J. Lowe
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/846
摘要： Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.
摘要翻译：可编程逻辑器件（PLD），包括自修复RAM电路，以及自动替换RAM阵列中有缺陷的列的方法。包括冗余列的RAM电路在PLD配置顺序期间使用内置的自检（BIST）过程进行测试。如果检测到有缺陷的列，则错误标志被存储在相关联的易失性存储器电路中。 BIST程序完成后，PLD配置过程继续。错误标志的存在导致配置数据绕过故障列，并直接传递到替换列。配置过程继续，直到电路的其余部分被配置，包括冗余列。在其他实施例中，独立于PLD配置过程启动BIST过程。当检测到有缺陷的列时，以对用户透明的方式，将数据从有缺陷的列分流到冗余列的用户操作恢复。

47. 发明申请

US20060230093A1 Digital signal processing circuit having a pattern detector circuit for convergent rounding 有权
标题翻译：具有用于收敛四舍五入的图案检测器电路的数字信号处理电路
公开(公告)号：US20060230093A1
公开(公告)日：2006-10-12
申请号：US11432847
申请日：2006-05-12
申请人： Bernard New , Jennifer Wong , James Simkins , Alvin Ching , John Thendean , Anna Wong , Vasisht Vadi
发明人： Bernard New , Jennifer Wong , James Simkins , Alvin Ching , John Thendean , Anna Wong , Vasisht Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.
摘要翻译：一种用于收敛舍入的集成电路（IC），包括：加法器电路，被配置为产生求和; 比较电路，被配置为将所述求和与输入模式进行逐位比较，使用掩码对所述比较进行逐位掩码，并将所述掩蔽比较结合以产生比较位; 以及舍入电路，用于至少部分地基于所述比较位对所述求和进行舍入。

48. 发明申请

US20060212499A1 Digital signal processing block having a wide multiplexer 有权
标题翻译：具有宽多路复用器的数字信号处理块
公开(公告)号：US20060212499A1
公开(公告)日：2006-09-21
申请号：US11433120
申请日：2006-05-12
申请人： Bernard New , Vasisht Vadi , Jennifer Wong , Alvin Ching , John Thendean , Anna Wong , James Simkins
发明人： Bernard New , Vasisht Vadi , Jennifer Wong , Alvin Ching , John Thendean , Anna Wong , James Simkins
IPC分类号： G06F15/00
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.
摘要翻译：一种数字信号处理块，具有：1）第一数字信号处理元件，包括：第一多路复用器的第一多路复用器，所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元，所述第一算术逻辑单元被配置为用于相加; 以及2）第二数字信号处理元件，包括：第二多路复用器的第二多路复用器，所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器，所述第二运算单元被配置为相加。

49. 发明授权

US06353341B1 Method and apparatus for discriminating against signal interference 有权
标题翻译：用于区分信号干扰的方法和装置
公开(公告)号：US06353341B1
公开(公告)日：2002-03-05
申请号：US09439844
申请日：1999-11-12
申请人： Austin H. Lesea , Peter H. Alfke , Jennifer Wong , Steven P. Young
发明人： Austin H. Lesea , Peter H. Alfke , Jennifer Wong , Steven P. Young
IPC分类号： G01R2902
CPC分类号： G01R31/31922 , G01R31/31937
摘要： A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.
摘要翻译：监视时钟信号以检测从第一逻辑状态到第二逻辑状态的转变。一旦检测到该转变，则在时间信号的后续转换在信号干扰最显着的预定时间段期间被忽略。在经过预定时间段之后，再次监视时钟信号以检测随后的状态转换。在一些实施例中，使用延迟电路来延迟时钟信号以产生延迟的时钟信号，该延迟时钟信号用于将时钟信号强制到第二逻辑状态达预定时间段。在一个实施例中，通过延迟电路上的一个或多个可选择的抽头，预定时间段是用户可选择的。

50. 发明授权

US5933025A Low voltage interface circuit with a high voltage tolerance 失效
标题翻译：具有高电压容差的低压接口电路
公开(公告)号：US5933025A
公开(公告)日：1999-08-03
申请号：US784163
申请日：1997-01-15
申请人： Scott S. Nance , Mohammad R. Tamjidi , Richard C. Li , Jennifer Wong , Hassan K. Bazargan
发明人： Scott S. Nance , Mohammad R. Tamjidi , Richard C. Li , Jennifer Wong , Hassan K. Bazargan
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/09429 , H03K19/00315 , H03K19/018521
摘要： A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin. In high impedance mode when the externally applied voltage at the I/O pin is sufficiently below the interface circuit supply voltage, the isolation circuit is driven to approximately the interface circuit supply voltage. In low impedance mode the isolation circuitry is disabled and the logic level at the data terminal is transmitted to the I/O pin. One embodiment of the present invention provides a buffered data path from the data terminal to the I/O pin.
摘要翻译：具有高电压公差的低压接口电路使得具有不同电源电平的器件能够有效耦合在一起，而不会有明显的漏电流或电路损坏。本发明的一个实施例包括三态控制电路，数据通路，参考电压电路和隔离电路。接口电路提供高阻抗接收模式。在这种模式下，当接口电路的I / O引脚施加的电压足够大于接口电路电源电压时，隔离电路会将电源与I / O引脚隔离开来。接口电路还保护所有的晶体管从栅极到体积，栅极到源极和漏极到大于指定电压的电压降，例如对于额定3V电源的3.6V，当高达5.5V被外部施加到 I / O引脚。在高阻抗模式下，当I / O引脚的外部施加电压足够低于接口电路电源电压时，隔离电路被驱动到大致接口电路电源电压。在低阻模式下，隔离电路被禁用，数据端子的逻辑电平被传输到I / O引脚。本发明的一个实施例提供从数据终端到I / O引脚的缓冲数据路径。

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