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41. 发明申请

US20080179658A1 METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE TRANSISTORS, NON-VOLATILE MEMORY TRANSISTORS, AND LOGIC TRANSISTORS 有权
标题翻译：制造具有高电压晶体管的半导体器件，非易失性存储器晶体管和逻辑晶体管的方法
公开(公告)号：US20080179658A1
公开(公告)日：2008-07-31
申请号：US11627725
申请日：2007-01-26
申请人： Rajesh A. Rao , Ramachandran Muralidhar
发明人： Rajesh A. Rao , Ramachandran Muralidhar
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L29/7887
摘要： A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate. After the second insulating layer is formed, a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate.
摘要翻译：在半导体衬底上制造半导体器件。第一绝缘层形成在半导体衬底上，用作半导体衬底的第一区域中的高电压晶体管的栅极电介质。在形成第一绝缘层之后，在半导体衬底上形成第二绝缘层，用作在衬底的第二区域中用作非易失性存储晶体管的栅极电介质。在形成第二绝缘层之后，在半导体衬底上形成第三绝缘层，用作衬底的第三区域中用于逻辑晶体管的栅极电介质。

42. 发明授权

US07364969B2 Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types 有权
标题翻译：用于集成嵌入式非易失性存储器件的形成与形成多个晶体管器件类型的半导体制造工艺
公开(公告)号：US07364969B2
公开(公告)日：2008-04-29
申请号：US11172728
申请日：2005-07-01
申请人： Erwin J. Prinz , Ramachandran Muralidhar
发明人： Erwin J. Prinz , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823857 , Y10S438/962
摘要： A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.
摘要翻译：半导体制造工艺包括在覆盖衬底的第一区域的隧道氧化物上形成多晶硅纳米晶体。沉积第二电介质覆盖在第一区域和第二区域上。在不提供覆盖第一区域中的第二电介质的任何保护层的情况下，进行额外的热氧化步骤而不氧化纳米晶体。然后将栅极电极膜沉积在第二电介质上并被图案化以形成第一和第二栅电极。第二电介质可以是退火的CVD氧化物。额外的热氧化可以包括通过干式氧化形成覆盖在半导体衬底的第三区域上的第三电介质。干燥氧化在第二区域中产生第二电介质下面的界面氧化硅。然后可以暴露基板的第四区域的上表面，并在第四区域的上表面上形成第四电介质。

43. 发明申请

US20070238278A1 METHOD OF SEPARATING A STRUCTURE IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中分离结构的方法
公开(公告)号：US20070238278A1
公开(公告)日：2007-10-11
申请号：US11278180
申请日：2006-03-31
申请人： Leo Mathew , Ramachandran Muralidhar , Veeraraghavan Dhandapani
发明人： Leo Mathew , Ramachandran Muralidhar , Veeraraghavan Dhandapani
IPC分类号： H01L21/3205
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L29/6653 , H01L29/66825 , H01L29/66833
摘要： Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.
摘要翻译：去除半导体器件中的一部分结构以分离结构。该结构具有两个不同高度的部分。在一个示例中，通过在与较高部分的侧壁相邻的下部形成隔离物来移除结构。然后在间隔件外部的结构上形成第二材料。移除间隔物，然后移除间隔物下面的部分以在该位置分离结构。在一个实施例中，在分离的结构中实现单独的通道区域。在其他实施例中，在分离的结构中实现单独的门结构。

44. 发明申请

US20070202645A1 METHOD FOR FORMING A DEPOSITED OXIDE LAYER 审中-公开
标题翻译：形成沉积氧化层的方法
公开(公告)号：US20070202645A1
公开(公告)日：2007-08-30
申请号：US11680121
申请日：2007-02-28
申请人： Tien Ying Luo , Lakshmanna Vishnubhotla , Tushar P. Merchant , Rajesh A. Rao , Ramachandran Muralidhar
发明人： Tien Ying Luo , Lakshmanna Vishnubhotla , Tushar P. Merchant , Rajesh A. Rao , Ramachandran Muralidhar
IPC分类号： H01L21/8242
CPC分类号： H01L29/7885 , B82Y10/00 , H01L21/02164 , H01L21/02271 , H01L21/02304 , H01L21/02337 , H01L21/31612 , H01L29/40117 , H01L29/42332 , H01L29/7883
摘要： An oxide layer formed by deposition is subject to a treatment process to repair bond defects of the oxide layer. In one embodiment, the layer is treated with nitric oxide. In one embodiment, a nitric oxide gas is flowed over the dielectric layer at an elevated temperature. In still another embodiment, the oxide layer is treated with fluorine. A layer is deposited over the oxide layer and a species containing fluorine is ion implanted into the layer. The wafer is heated where the species is driven to the oxide layer.
摘要翻译：通过沉积形成的氧化物层经受处理工艺以修复氧化物层的结合缺陷。在一个实施方案中，该层用一氧化氮处理。在一个实施方案中，一氧化氮气体在升高的温度下流过电介质层。在另一个实施方案中，用氟处理氧化物层。在氧化物层上沉积一层，并且将含氟物质离子注入到该层中。加热晶片，将物质驱动到氧化物层。

45. 发明授权

US07186616B2 Method of removing nanoclusters in a semiconductor device 有权
标题翻译：在半导体器件中去除纳米团簇的方法
公开(公告)号：US07186616B2
公开(公告)日：2007-03-06
申请号：US11082094
申请日：2005-03-16
申请人： Rajesh A. Rao , Ramachandran Muralidhar , Robert F. Steimle
发明人： Rajesh A. Rao , Ramachandran Muralidhar , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/30604 , H01L21/3065 , H01L29/42332 , H01L29/66825
摘要： A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400–900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device at a temperature in a range of 400–900 degrees Celsius. In another form, a method for removing the nanoclusters includes implanting germanium or nitrogen into the nanociusters, etching a selected portion of the insulating layer using a dry etch process, and removing the layer of nanoclusters using a wet etch process that is selective to an insulating layer.
摘要翻译：一种用于从半导体器件中去除纳米团簇的方法包括：在400-900摄氏度的温度范围内蚀刻绝缘层的选定部分，使还原气体在半导体器件上流动，并使包含卤素的气体流过半导体器件在400-900摄氏度的温度范围内。在另一种形式中，用于去除纳米团簇的方法包括将锗或氮注入到纳米过滤器中，使用干蚀刻工艺蚀刻绝缘层的选定部分，以及使用对绝缘选择性的湿蚀刻工艺去除纳米团簇层层。

46. 发明申请

US20060211206A1 Electronic devices including non-volatile memory and processes for forming the same 有权
标题翻译：包括非易失性存储器的电子设备及其形成工艺
公开(公告)号：US20060211206A1
公开(公告)日：2006-09-21
申请号：US11084283
申请日：2005-03-18
申请人： Rajesh Rao , Ramachandran Muralidhar
发明人： Rajesh Rao , Ramachandran Muralidhar
IPC分类号： H01L21/8234 , H01L21/76
CPC分类号： H01L27/11526 , B82Y10/00 , H01L27/105 , H01L27/11546
摘要： A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By protecting the field isolation regions within the NVM array and other regions while gate dielectric layer are formed, the field isolation regions may be exposed to as little as one oxide etch between the time any of the gate dielectric layers are formed the time such gate dielectric layers are covered by gate electrode layers. The process helps to reduce field isolation erosion and reduce problems associated therewith.
摘要翻译：可以执行用于形成电子器件的工艺，使得可以在电子器件的每个区域内形成少至一个栅极电层。在一个实施例中，电子设备可以包括NVM阵列和具有不同栅介电层的其它区域。通过在形成栅介质层的同时保护NVM阵列和其它区域内的场隔离区域，在形成任何栅极电介质层的时间之间，场隔离区可能暴露于少至一个氧化物蚀刻，层被栅极电极层覆盖。该过程有助于减少场隔离侵蚀并减少与之相关的问题。

47. 发明申请

US20060211199A1 Method of removing nanoclusters in a semiconductor device 有权
标题翻译：在半导体器件中去除纳米团簇的方法
公开(公告)号：US20060211199A1
公开(公告)日：2006-09-21
申请号：US11082094
申请日：2005-03-16
申请人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle
发明人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/30604 , H01L21/3065 , H01L29/42332 , H01L29/66825
摘要： A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400-900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device a temperature in a range of 400-900 degrees Celsius. In another form, a method for removing the nanoclusters includes implanting germanium or nitrogen into the nanoclusters, etching a selected portion of the insulating layer using a dry etch process, and removing the layer of nanoclusters using a wet etch process that is selective to an insulating layer.
摘要翻译：一种用于从半导体器件中去除纳米团簇的方法包括：在400-900摄氏度的温度范围内蚀刻绝缘层的选定部分，使还原气体在半导体器件上流动，并使包含卤素的气体流过半导体器件温度在400-900摄氏度的范围内。在另一种形式中，用于去除纳米团簇的方法包括将锗或氮注入到纳米团簇中，使用干蚀刻工艺蚀刻绝缘层的选定部分，以及使用对绝缘选择性的湿蚀刻工艺去除纳米团簇层层。

48. 发明授权

US07109550B2 Semiconductor fabrication process with asymmetrical conductive spacers 有权
标题翻译：具有不对称导电间隔物的半导体制造工艺
公开(公告)号：US07109550B2
公开(公告)日：2006-09-19
申请号：US11036860
申请日：2005-01-13
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L29/792
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823468 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/7842 , Y10S257/90
摘要： A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.
摘要翻译：半导体工艺和所得晶体管包括在栅电极（116）的任一侧上形成导电延伸间隔物（146,150）。导电延伸部（146,150）和栅电极116被独立地掺杂，使得每个结构可以是n型或p型。源极/漏极区域（156）被植入在间隔物（146,150）的任一侧上。间隔物（146,150）可以通过使用第一成角度的植入物（132）来掺杂第一延伸间隔物（146）和第二成角度的植入物（140）以掺杂第二间隔物（150）来独立地掺杂。在一个实施例中，使用不同掺杂的延伸间隔物（146,150）消除了对阈值调整通道植入物的需要。

49. 发明申请

US20060194438A1 METHOD OF FORMING A NANOCLUSTER CHARGE STORAGE DEVICE 有权
标题翻译：形成纳米碳管充电储存装置的方法
公开(公告)号：US20060194438A1
公开(公告)日：2006-08-31
申请号：US10876820
申请日：2004-06-25
申请人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle , Gowrishankar Chindalore
发明人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle , Gowrishankar Chindalore
IPC分类号： H01L21/302 , H01L31/112 , H01L21/36
CPC分类号： H01L27/11546 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42332
摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
摘要翻译：通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。第二形成的含多晶硅的层从包含多个存储单元的区域中去除。在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。

50. 发明申请

US20060189079A1 Method of forming nanoclusters 审中-公开
标题翻译：形成纳米团簇的方法
公开(公告)号：US20060189079A1
公开(公告)日：2006-08-24
申请号：US11065519
申请日：2005-02-24
申请人： Tushar Merchant , Ramachandran Muralidhar , Rajesh Rao , Matthew Stoker , Sherry Straub
发明人： Tushar Merchant , Ramachandran Muralidhar , Rajesh Rao , Matthew Stoker , Sherry Straub
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/40114 , H01L29/66825
摘要： A method for forming nanoclusters includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate, exposing the semiconductor substrate to a first flux of atoms to form first nuclei on the dielectric layer, exposing the first nuclei to a first inert atmosphere after exposing the semiconductor substrate to the first flux, and exposing the semiconductor substrate to a second flux of atoms to form second nuclei after exposing the first nuclei to an inert atmosphere.
摘要翻译：一种形成纳米团簇的方法包括提供半导体衬底; 在所述半导体衬底上形成电介质层，将所述半导体衬底暴露于所述第一原子通量，以在所述电介质层上形成第一核，在将所述半导体衬底暴露于所述第一焊剂之后，将所述第一核暴露于第一惰性气氛，半导体衬底到第二个原子通量，以在将第一核暴露于惰性气氛之后形成第二核。

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