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41. 发明申请

US20050289490A1 Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits 有权
标题翻译：用于单片硅基光电路的设计，仿真和验证的综合方法
公开(公告)号：US20050289490A1
公开(公告)日：2005-12-29
申请号：US11159283
申请日：2005-06-22
申请人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
发明人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译：计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。一旦行为逻辑设计完成，结果将被合并并共同模拟。为电路中的每种不同类型的元件开发和验证物理布局设计。然后将单独的物理布局共同验证，以评估整体物理设计的属性。将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。

42. 发明申请

US20050094939A1 Interfacing multiple wavelength sources to thin optical waveguides utilizing evanescent coupling 有权
标题翻译：使用ev逝耦合将多个波长源连接到薄光波导上
公开(公告)号：US20050094939A1
公开(公告)日：2005-05-05
申请号：US10935146
申请日：2004-09-07
申请人： Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine Yanushefski
发明人： Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine Yanushefski
IPC分类号： G02B20060101 , G02B6/34
CPC分类号： G02B6/12007 , G02B6/124 , G02B6/34
摘要： An arrangement for achieving and maintaining high efficiency coupling of light between a multi-wavelength optical signal and a relatively thin (e.g., sub-micron) silicon optical waveguide uses a prism coupler in association with an evanescent coupling layer. A grating structure having a period less than the wavelengths of transmission is formed in the coupling region (either formed in the silicon waveguide, evanescent coupling layer, prism coupler, or any combination thereof) so as to increase the effective refractive index “seen” by the multi-wavelength optical signal in the area where the beam exiting/entering the prism coupler intercepts the waveguide surface (referred to as the “prism coupling surface”). The period and/or duty cycle of the grating can be controlled to modify the effective refractive index profile in the direction away from the coupling region so as to reduce the effective refractive index from the relatively high value useful in multi-wavelength coupling to the lower value associated with maintaining confinement of the optical signals within the surface waveguide structure, thus reducing reflections along the transition region.
摘要翻译：用于实现和维持多波长光信号和较薄（例如亚微米）硅光波导之间的高效率耦合的布置使用与渐逝耦合层相关联的棱镜耦合器。在耦合区域（形成在硅波导，ev逝耦合层，棱镜耦合器或其任何组合中）形成具有小于透射波长的周期的光栅结构，以便通过“看到”来提高有效折射率离开/进入棱镜耦合器的光束截取波导表面（称为“棱镜耦合表面”）的区域中的多波长光信号。可以控制光栅的周期和/或占空比以在远离耦合区域的方向上改变有效折射率分布，以便将有效折射率从在多波长耦合中的有用折射率降低到较低的值与保持表面波导结构内的光信号的限制相关联的值，从而减少沿着过渡区域的反射。

43. 发明申请

US20050094938A1 External grating structures for interfacing wavelength-division-multiplexed optical sources with thin optical waveguides 有权
标题翻译：用于将波分复用光源与薄光波导接口连接的外部光栅结构
公开(公告)号：US20050094938A1
公开(公告)日：2005-05-05
申请号：US10935145
申请日：2004-09-07
申请人： Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine Yanushefski
发明人： Margaret Ghiron , Prakash Gothoskar , Robert Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine Yanushefski
IPC分类号： G02B20060101 , G02B6/34
CPC分类号： G02B6/12007 , G02B6/122 , G02B6/29311 , G02B6/34
摘要： A coupling arrangement for allowing multiple wavelengths to be coupled into and out of a relatively thin silicon optical waveguide layer utilizes a diffractive optical element, in the form of a volume phase grating, in combination with a prism coupling structure. The diffractive optical element is formed to comprise a predetermined modulation index sufficient to diffract the various wavelengths through angles associated with improving the coupling efficiency of each wavelength into the silicon waveguide. The diffractive optical element may be formed as a separate element, or formed as an integral part of the coupling facet of the prism coupler.
摘要翻译：用于允许多个波长耦合到相对薄的硅光波导层中的耦合布置利用体积相位光栅的形式的衍射光学元件与棱镜耦合结构组合。衍射光学元件被形成为包括足以将各种波长衍射成与提高每个波长到硅波导的耦合效率相关联的角度的预定调制指数。衍射光学元件可以形成为单独的元件，或者形成为棱镜耦合器的耦合面的整体部分。

44. 发明授权

US08803269B2 Wafer scale packaging platform for transceivers 有权
标题翻译：收发器晶圆级封装平台
公开(公告)号：US08803269B2
公开(公告)日：2014-08-12
申请号：US13463408
申请日：2012-05-03
申请人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
发明人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
IPC分类号： H01L31/0232 , H01L29/40 , H01L23/053 , H01L23/12
CPC分类号： H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
摘要翻译：光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义分离光学元件之间的光信号路径。实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

45. 发明申请

US20110221019A1 Silicon-Based Schottky Barrier Detector With Improved Responsivity 有权
标题翻译：具有改善响应性的硅基肖特基势垒检测器
公开(公告)号：US20110221019A1
公开(公告)日：2011-09-15
申请号：US13038470
申请日：2011-03-02
申请人： Vipulkumar Patel , Prakash Gothoskar , Mark Webster , Christopher J. Lang
发明人： Vipulkumar Patel , Prakash Gothoskar , Mark Webster , Christopher J. Lang
IPC分类号： H01L31/108
CPC分类号： H01L31/101 , H01L31/1085
摘要： A planar, waveguide-based silicon Schottky barrier photodetector includes a third terminal in the form of a field plate to improve the responsivity of the detector. Preferably, a silicide used for the detection region is formed during a processing step where other silicide contact regions are being formed. The field plate is preferably formed as part of the first or second layer of CMOS metallization and is controlled by an applied voltage to modify the electric field in the vicinity of the detector's silicide layer. By modifying the electric field, the responsivity of the device is “tuned” so as to adjust the momentum of “hot” carriers (electrons or holes, depending on the conductivity of the silicon) with respect to the Schottky barrier of the device. The applied potential functions to align with the direction of momentum of the “hot” carriers in the preferred direction “normal” to the silicon-silicide interface, allowing for an increased number to move over the Schottky barrier and add to the generated photocurrent.
摘要翻译：平面的基于波导的硅肖特基势垒光电检测器包括场板形式的第三端子，以提高检测器的响应度。优选地，在其中形成其它硅化物接触区域的处理步骤期间形成用于检测区域的硅化物。场板优选地形成为第一或第二CMOS金属化层的一部分，并且通过施加的电压来控制，以修改检测器硅化物层附近的电场。通过修改电场，器件的响应度被“调谐”，以相对于器件的肖特基势垒调节“热”载流子（电子或空穴，取决于硅的导电性）的动量。所施加的电位功能与“硅”载体的优势方向“正常”硅硅化物界面的动量方向相一致，允许增加的数量移动到肖特基势垒上并增加产生的光电流。

46. 发明申请

US20110127633A1 Slotted Configuration for Optimized Placement of Micro-Components using Adhesive Bonding 有权
标题翻译：用于使用粘合剂粘合优化微组件放置的开槽配置
公开(公告)号：US20110127633A1
公开(公告)日：2011-06-02
申请号：US12955011
申请日：2010-11-29
申请人： Mary Nadeau , Vipulkumar Patel , Prakash Gothoskar , John Fangman , John Matthew Fangman , Mark Webster
发明人： Mary Nadeau , Vipulkumar Patel , Prakash Gothoskar , John Fangman , John Matthew Fangman , Mark Webster
IPC分类号： H01L27/12 , B32B3/30 , H01L27/04
CPC分类号： G02B7/025 , G02B6/4228 , G02B6/4239 , G02B7/003 , H01L23/345 , H01L23/544 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2223/54426 , H01L2224/26175 , H01L2224/2919 , H01L2224/32225 , H01L2224/83121 , H01L2224/83143 , H01L2224/83192 , H01L2224/83234 , H01L2224/83385 , H01L2224/83862 , H01L2924/14 , Y10T428/24479 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要： An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
摘要翻译：用于改善组件中微组件的粘合附着的装置利用形成在用于支撑微组件的衬底顶表面中的多个平行布置的槽。这些槽用于控制粘合剂“点”的流动和“形状”，以便将微组件快速且精确地附着在基板的表面上。在衬底的表面中形成（优选地，蚀刻）狭槽，使其自身具有从一个衬底到另一个衬底的可再现精度。其它槽（“通道”）可以与结合槽结合形成，使得外来粘合剂材料将流入这些通道并且不会扩散到不需要的区域。

47. 发明授权

US07701985B2 SOI-based tunable laser 有权
标题翻译：基于SOI的可调谐激光器
公开(公告)号：US07701985B2
公开(公告)日：2010-04-20
申请号：US12291246
申请日：2008-11-06
申请人： Mark Webster , David Piede , Prakash Gothoskar
发明人： Mark Webster , David Piede , Prakash Gothoskar
IPC分类号： H01S3/10 , H01S3/13
CPC分类号： H01S5/141 , H01S5/021 , H01S5/02248 , H01S5/02268 , H01S5/06256
摘要： A silicon-on-insulator (SOI)-based tunable laser is formed to include the gain medium (such as a semiconductor optical amplifier) disposed within a cavity formed within the SOI substrate. A tunable wavelength reflecting element and associated phase matching element are formed on the surface of the SOI structure, with optical waveguides formed in the surface SOI layer providing the communication between these components. The tunable wavelength element is controlled to adjust the optical wavelength. Separate discrete lensing elements may be disposed in the cavity with the gain medium, providing efficient coupling of the optical signal into the SOI waveguides. Alternatively, the gain medium itself may be formed to include spot converting tapers on its endfaces, the tapers used to provide mode matching into the associated optical waveguides.
摘要翻译：形成绝缘体上硅（SOI）的可调谐激光器以包括设置在形成于SOI衬底内的空腔内的增益介质（例如半导体光放大器）。在SOI结构的表面上形成可调波长反射元件和相关的相位匹配元件，其中形成在表面SOI层中的光波导提供这些部件之间的连通。可调波长元件被控制以调节光学波长。单独的离散透镜元件可以用增益介质设置在空腔中，从而提供光信号到SOI波导的有效耦合。或者，增益介质本身可以被形成为包括其端面上的点变换锥度，用于向相关联的光波导提供模式匹配的锥度。

48. 发明申请

US20090162013A1 Coupling between free space and optical waveguide using etched coupling surfaces 有权
标题翻译：使用蚀刻的耦合表面在自由空间和光波导之间耦合
公开(公告)号：US20090162013A1
公开(公告)日：2009-06-25
申请号：US12316540
申请日：2008-12-11
申请人： Mark Webster , Vipulkumar Patel , Mary Nadeau , Prakash Gothoskar , David Piede
发明人： Mark Webster , Vipulkumar Patel , Mary Nadeau , Prakash Gothoskar , David Piede
IPC分类号： G02B6/42
CPC分类号： G02B6/32 , G02B6/305 , G02B6/327
摘要： A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.
摘要翻译：使用基于等离子体的蚀刻工艺来将支撑光波导的光学基板的端面特别地成形为轮廓刻面，这将提高波导与自由空间光信号之间的耦合效率。使用标准光刻技术对光学端面小平面进行图案化和刻蚀的能力允许形成任何所需的刻面几何形状，并跨越制造的整组组件在晶片的表面上复制。可以使用适当限定的光刻掩模将透镜蚀刻到端面中，相对于光波导的参数和传播的自由空间信号选择透镜的焦点。或者，可以沿着端面形成成角度的小面，其角度足以将反射/散射信号重新引导远离光轴。

49. 发明授权

US07269809B2 Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits 有权
标题翻译：用于单片硅基光电路的设计，仿真和验证的综合方法
公开(公告)号：US07269809B2
公开(公告)日：2007-09-11
申请号：US11159283
申请日：2005-06-22
申请人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
发明人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译：计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。一旦行为逻辑设计完成，结果将被合并并共同模拟。为电路中的每种不同类型的元件开发和验证物理布局设计。然后将单独的物理布局共同验证，以评估整体物理设计的属性。将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。

50. 发明申请

US20060140645A1 High-speed, silicon-based electro-optic modulator with feedback control 有权
标题翻译：具有反馈控制功能的高速硅基电光调制器
公开(公告)号：US20060140645A1
公开(公告)日：2006-06-29
申请号：US11362305
申请日：2006-02-22
申请人： Kalpendu Shastri , Prakash Gothoskar , Margaret Ghiron , Vipulkumar Patel , Robert Montgomery , Soham Pathak , Katherine Yanushefski
发明人： Kalpendu Shastri , Prakash Gothoskar , Margaret Ghiron , Vipulkumar Patel , Robert Montgomery , Soham Pathak , Katherine Yanushefski
IPC分类号： H04B10/04 , H04B10/12
CPC分类号： G02F1/025 , G02F1/0121 , G02F1/225 , G02F2001/0152 , H04B10/505 , H04B10/58
摘要： An electro-optic modulator arrangement for achieving switching speeds greater than 1 Gb/s utilizes pre-emphasis pulses to accelerate the change in refractive index of the optical waveguide used to form the electro-optic modulator. In one embodiment, a feedback loop may be added to use a portion of the modulated optical output signal to adjust the magnitude and duration of the pre-emphasis pulses, as well as the various reference levels used for modulated. For free carrier-based electro-optic modulators, including silicon-based electro-optic modulators, the pre-emphasis pulses are used to accelerate the movement of free carriers at the transitions between input signal data values.
摘要翻译：用于实现大于1Gb / s的开关速度的电光调制器装置利用预加重脉冲来加速用于形成电光调制器的光波导的折射率变化。在一个实施例中，可以添加反馈回路以使用调制的光输出信号的一部分来调整预加重脉冲的幅度和持续时间以及用于调制的各种参考电平。对于基于硅的电光调制器的自由载体的电光调制器，预加重脉冲用于加速在输入信号数据值之间的转变处的自由载流子的移动。

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