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41. 发明授权

US06730566B2 Method for non-thermally nitrided gate formation for high voltage devices 有权
标题翻译：高压器件非热氮化栅极形成方法
公开(公告)号：US06730566B2
公开(公告)日：2004-05-04
申请号：US10264729
申请日：2002-10-04
申请人： Hiroaki Niimi , Rajesh Khamankar , Husam N. Alshareef
发明人： Hiroaki Niimi , Rajesh Khamankar , Husam N. Alshareef
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , Y10S438/92
摘要： A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices to mitigate leakage associated with the high voltage transistor devices. The nitridation of the gate dielectric layer damages the surface of the gate dielectric layer. The damaged surface of the gate dielectric layer is removed by a relatively low temperature re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process and mitigates film densification, such that the structure can be readily etched by standard etching chemicals in subsequent processing.
摘要翻译：提供了用于高压晶体管器件的非热氮化栅极形成的方法。非热氮化栅极形成可用于双厚度栅极电介质结构的形成。非热氮化栅极形成包括氮化以将氮原子引入到高压晶体管器件的栅极介电层中，以减轻与高压晶体管器件相关的泄漏。栅极电介质层的氮化破坏了栅极电介质层的表面。通过相对较低温度的再氧化工艺去除栅介电层的受损表面。低温再氧化工艺在随后的光致抗蚀剂剥离过程中使氮损失最小化并减轻膜致密化，使得结构可以在随后的处理中通过标准蚀刻化学品容易地蚀刻。

42. 发明授权

US06632747B2 Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile 有权
标题翻译：用于均匀氮分布的超薄二氧化硅层的氨退火方法
公开(公告)号：US06632747B2
公开(公告)日：2003-10-14
申请号：US09885600
申请日：2001-06-20
申请人： Hiroaki Niimi , Douglas T. Grider , Rajesh Khamankar , Sunil Hattangady
发明人： Hiroaki Niimi , Douglas T. Grider , Rajesh Khamankar , Sunil Hattangady
IPC分类号： H01L2131
CPC分类号： H01L21/02332 , H01L21/0214 , H01L21/02164 , H01L21/02323 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% 02); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.
摘要翻译：本发明的一个实施例是通过提供具有半导体表面的衬底来形成超薄电介质层的方法; 在半导体表面上形成含氧层; 将含氧层暴露于含氮等离子体以在整个含氧层中产生均匀的氮分布; 并重新氧化和退火该层以稳定氮分布，治愈等离子体诱导的损伤并降低界面缺陷密度。该退火步骤选自一组四种再氧化技术：连续在H 2和N 2（优选小于20％H 2）的混合物中进行退火，然后将O 2和N 2（优选小于20％的O 2）的混合物进行退火;通过尖峰状温度升高（优选小于20％（优选为N 2 / O 2或N 2 O / H 2）;通过在减压下的氨中快速热加热（优选在600至1000℃下，对于 5至60秒）;在800至1050℃下在氧化剂/氢气混合物（优选N 2 O与1％H 2）中退火5至60秒。

43. 发明授权

US08021990B2 Gate structure and method 有权
标题翻译：门结构和方法
公开(公告)号：US08021990B2
公开(公告)日：2011-09-20
申请号：US12421036
申请日：2009-04-09
申请人： Antonio L. P. Rotondaro , Luigi Colombo , Mark R Visokay , Rajesh Khamankar , Douglas E Mercer
发明人： Antonio L. P. Rotondaro , Luigi Colombo , Mark R Visokay , Rajesh Khamankar , Douglas E Mercer
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823857 , H01L21/823871 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
摘要翻译：一种MOSFET结构，包括在栅极材料沉积之前具有栅极电介质的氮化处理的硅酸盐栅极电介质。

44. 发明授权

US07345001B2 Gate dielectric having a flat nitrogen profile and method of manufacture therefor 有权
标题翻译：具有平坦氮分布的栅极电介质及其制造方法
公开(公告)号：US07345001B2
公开(公告)日：2008-03-18
申请号：US10875482
申请日：2004-06-24
申请人： Hiroaki Niimi , Husam N. Alshareef , Rajesh Khamankar , Toan Tran
发明人： Hiroaki Niimi , Husam N. Alshareef , Rajesh Khamankar , Toan Tran
IPC分类号： H01L29/72
CPC分类号： H01L21/3115 , H01L21/0214 , H01L21/02329 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L29/512 , H01L29/518 , H01L29/6656
摘要： The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.
摘要翻译：本发明提供一种具有平坦氮分布的栅极电介质及其制造方法，以及制造包含平坦氮分布的集成电路的方法。在一个实施例中，制造栅极电介质的方法包括在衬底（310）上形成栅极电介质层（410），并对栅极电介质层（410）施加含氮等离子体工艺（510），其中含氮等离子体工艺（510）的氦与氮的比例为3:1或更高。

45. 发明申请

US20070207572A1 CMOS Device Having Different Amounts of Nitrogen in the NMOS Gate Dielectric Layers and PMOS Gate Dielectric Layers 有权
标题翻译：在NMOS栅极电介质层和PMOS栅介质层中具有不同氮含量的CMOS器件
公开(公告)号：US20070207572A1
公开(公告)日：2007-09-06
申请号：US11745930
申请日：2007-05-08
申请人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
IPC分类号： H01L21/82
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

46. 发明申请

US20060043369A1 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers 有权
标题翻译： CMOS器件在NMOS栅极电介质层和PMOS栅极电介质层中具有不同量的氮
公开(公告)号：US20060043369A1
公开(公告)日：2006-03-02
申请号：US10927858
申请日：2004-08-27
申请人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
IPC分类号： H01L29/76
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

47. 发明申请

US20050285211A1 Gate dielectric having a flat nitrogen profile and method of manufacture therefor 有权
标题翻译：具有平坦氮分布的栅极电介质及其制造方法
公开(公告)号：US20050285211A1
公开(公告)日：2005-12-29
申请号：US10875482
申请日：2004-06-24
申请人： Hiroaki Niimi , Husam Alshareef , Rajesh Khamankar , Toan Tran
发明人： Hiroaki Niimi , Husam Alshareef , Rajesh Khamankar , Toan Tran
IPC分类号： H01L21/28 , H01L29/51 , H01L29/76
CPC分类号： H01L21/3115 , H01L21/0214 , H01L21/02329 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L29/512 , H01L29/518 , H01L29/6656
摘要： The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.
摘要翻译：本发明提供一种具有平坦氮分布的栅极电介质及其制造方法，以及制造包含平坦氮分布的集成电路的方法。在一个实施例中，制造栅极电介质的方法包括在衬底（310）上形成栅极电介质层（410），并对栅极电介质层（410）施加含氮等离子体工艺（510），其中含氮等离子体工艺（510）的氦与氮的比例为3:1或更高。

48. 发明授权

US06780719B2 Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures 有权
标题翻译：使用氧化剂/氢混合物退火超薄，高质量的栅氧化层的方法
公开(公告)号：US06780719B2
公开(公告)日：2004-08-24
申请号：US09885744
申请日：2001-06-20
申请人： Hiroaki Niimi , Rajesh Khamankar , James J. Chambers , Sunil Hattangady , Antonio L. P. Rotondaro
发明人： Hiroaki Niimi , Rajesh Khamankar , James J. Chambers , Sunil Hattangady , Antonio L. P. Rotondaro
IPC分类号： H01L21336
CPC分类号： H01L21/02332 , H01L21/0214 , H01L21/02164 , H01L21/02323 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.
摘要翻译：本发明的一个实施例是形成超薄介电层的方法，该方法包括以下步骤：提供具有半导体表面的基板; 在半导体表面上形成含氧层; 将含氧层暴露于含氮等离子体以在整个含氧层中产生均匀的氮分布; 并重新氧化和退火层以稳定氮分布，治愈等离子体诱导的损伤并降低界面缺陷密度。该退火步骤选自四种再氧化技术：在H2和N2的混合物中连续退火（优选小于20％H 2），然后是O 2和N 2（优选小于20％O 2）的混合物;通过尖峰状升温（优选在1000至1150℃下优选小于1秒）在氮气中退火（优选为N 2 / O 2或N 2 O / H 2）;通过在减压的氨中快速热加热（优选在600至1000℃下5至60秒）进行退火;在氧化剂/氢气混合物（优选N 2 O 1％H 2）在800至1050℃下进行5至60秒。

49. 发明授权

US06342420B1 Hexagonally symmetric integrated circuit cell 有权
标题翻译：六边形对称集成电路单元
公开(公告)号：US06342420B1
公开(公告)日：2002-01-29
申请号：US09542002
申请日：2000-04-03
申请人： Akitoshi Nishimura , Yasutoshi Okuno , Rajesh Khamankar , Shane R. Palmer
发明人： Akitoshi Nishimura , Yasutoshi Okuno , Rajesh Khamankar , Shane R. Palmer
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10805 , Y10S257/905
摘要： An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.
摘要翻译：用于制造六边形对称单元（例如，动态随机存取存储单元（100））的装置和方法。电池可以包括位线触点（38），六边形围绕位线触点（38）的存储节点触点（32），也围绕位线触点（38）的存储节点（36），其中一部分形成字段效应晶体管栅极。位线触点（38）和存储节点触点（32）之间的大距离在光刻期间引起很大的问题，因为使用Levenson Phaseshift时很难实现暗区。因为Levenson Phaseshift取决于附近特征之间的波浪消除，通常被称为破坏性干扰，所以模式的最终可印刷性主要是对称性和分离距离的函数。当图案中的非对称性发生时，结果是在打印步骤期间，场的更弱的取消（即，特征之间）和图像对比度的大的损失和焦点的深度。最终结果是通过本文公开的几何修改可以显着地减少增加设备故障的缺陷。

50. 发明授权

US6166408A Hexagonally symmetric integrated circuit cell 有权
标题翻译：六边形对称集成电路单元
公开(公告)号：US6166408A
公开(公告)日：2000-12-26
申请号：US216251
申请日：1998-12-18
申请人： Akitoshi Nishimura , Yasutoshi Okuno , Rajesh Khamankar , Shane R. Palmer
发明人： Akitoshi Nishimura , Yasutoshi Okuno , Rajesh Khamankar , Shane R. Palmer
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/10805 , Y10S257/905
摘要： An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.
摘要翻译：用于制造六边形对称单元（例如，动态随机存取存储单元（100））的装置和方法。电池可以包括位线触点（38），六边形围绕位线触点（38）的存储节点触点（32），也围绕位线触点（38）的存储节点（36），其中一部分形成字段效应晶体管栅极。位线触点（38）和存储节点触点（32）之间的大距离在光刻期间引起很大的问题，因为当使用Levenson Phaseshift时，很难实现暗区。因为Levenson Phaseshift取决于附近特征之间的波浪消除，通常被称为破坏性干扰，所以模式的最终可印刷性主要是对称性和分离距离的函数。当图案中的非对称性发生时，结果是在打印步骤期间，场的更弱的取消（即，特征之间）和图像对比度的大的损失和焦点的深度。最终结果是通过本文公开的几何修改可以显着地减少增加设备故障的缺陷。

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