专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06730566B2 Method for non-thermally nitrided gate formation for high voltage devices 有权
标题翻译：高压器件非热氮化栅极形成方法
公开(公告)号：US06730566B2
公开(公告)日：2004-05-04
申请号：US10264729
申请日：2002-10-04
申请人： Hiroaki Niimi , Rajesh Khamankar , Husam N. Alshareef
发明人： Hiroaki Niimi , Rajesh Khamankar , Husam N. Alshareef
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , Y10S438/92
摘要： A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices to mitigate leakage associated with the high voltage transistor devices. The nitridation of the gate dielectric layer damages the surface of the gate dielectric layer. The damaged surface of the gate dielectric layer is removed by a relatively low temperature re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process and mitigates film densification, such that the structure can be readily etched by standard etching chemicals in subsequent processing.
摘要翻译：提供了用于高压晶体管器件的非热氮化栅极形成的方法。非热氮化栅极形成可用于双厚度栅极电介质结构的形成。非热氮化栅极形成包括氮化以将氮原子引入到高压晶体管器件的栅极介电层中，以减轻与高压晶体管器件相关的泄漏。栅极电介质层的氮化破坏了栅极电介质层的表面。通过相对较低温度的再氧化工艺去除栅介电层的受损表面。低温再氧化工艺在随后的光致抗蚀剂剥离过程中使氮损失最小化并减轻膜致密化，使得结构可以在随后的处理中通过标准蚀刻化学品容易地蚀刻。

2. 发明授权

US07345001B2 Gate dielectric having a flat nitrogen profile and method of manufacture therefor 有权
标题翻译：具有平坦氮分布的栅极电介质及其制造方法
公开(公告)号：US07345001B2
公开(公告)日：2008-03-18
申请号：US10875482
申请日：2004-06-24
申请人： Hiroaki Niimi , Husam N. Alshareef , Rajesh Khamankar , Toan Tran
发明人： Hiroaki Niimi , Husam N. Alshareef , Rajesh Khamankar , Toan Tran
IPC分类号： H01L29/72
CPC分类号： H01L21/3115 , H01L21/0214 , H01L21/02329 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L29/512 , H01L29/518 , H01L29/6656
摘要： The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.
摘要翻译：本发明提供一种具有平坦氮分布的栅极电介质及其制造方法，以及制造包含平坦氮分布的集成电路的方法。在一个实施例中，制造栅极电介质的方法包括在衬底（310）上形成栅极电介质层（410），并对栅极电介质层（410）施加含氮等离子体工艺（510），其中含氮等离子体工艺（510）的氦与氮的比例为3:1或更高。

3. 发明授权

US07402524B2 Post high voltage gate oxide pattern high-vacuum outgas surface treatment 有权
标题翻译：后高压栅氧化层图案高真空脱气表面处理
公开(公告)号：US07402524B2
公开(公告)日：2008-07-22
申请号：US11292883
申请日：2005-12-02
申请人： Brian K. Kirkpatrick , Rajesh Khamankar , Malcolm J. Bevan , April Gurba , Husam N. Alshareef , Clinton L. Montgomery , Mark H. Somervell
发明人： Brian K. Kirkpatrick , Rajesh Khamankar , Malcolm J. Bevan , April Gurba , Husam N. Alshareef , Clinton L. Montgomery , Mark H. Somervell
IPC分类号： H01L21/00
CPC分类号： H01L21/28202 , H01L21/02046 , H01L21/26506 , H01L21/28167 , H01L21/31105 , H01L21/31111 , H01L21/31144 , H01L21/3185 , H01L21/823462 , H01L29/518
摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.
摘要翻译：本发明提供一种制造双栅极半导体器件的方法。在一个方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化在暴露的氮化高压栅极电介质层上留下促进剂残留物，并将暴露的氮化高压电介质施加到高真空以除去促进剂残余物。

4. 发明授权

US07018925B2 Post high voltage gate oxide pattern high-vacuum outgas surface treatment 有权
标题翻译：后高压栅氧化层图案高真空脱气表面处理
公开(公告)号：US07018925B2
公开(公告)日：2006-03-28
申请号：US10752885
申请日：2004-01-06
申请人： Brian K. Kirkpatrick , Rajesh Khamankar , Malcolm J. Bevan , April Gurba , Husam N. Alshareef , Clinton L. Montgomery , Mark H. Somervell
发明人： Brian K. Kirkpatrick , Rajesh Khamankar , Malcolm J. Bevan , April Gurba , Husam N. Alshareef , Clinton L. Montgomery , Mark H. Somervell
IPC分类号： H01L21/302
CPC分类号： H01L21/28202 , H01L21/02046 , H01L21/26506 , H01L21/28167 , H01L21/31105 , H01L21/31111 , H01L21/31144 , H01L21/3185 , H01L21/823462 , H01L29/518
摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.
摘要翻译：本发明提供一种制造双栅极半导体器件的方法。在一个方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化在暴露的氮化高压栅极电介质层上留下促进剂残留物，并将暴露的氮化高压电介质施加到高真空以除去促进剂残余物。

5. 发明授权

US07682988B2 Thermal treatment of nitrided oxide to improve negative bias thermal instability 有权
标题翻译：氮化氧化物的热处理以改善负偏压热不稳定性
公开(公告)号：US07682988B2
公开(公告)日：2010-03-23
申请号：US10930230
申请日：2004-08-31
申请人： Husam N. Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy A. Chancellor , Anand Krishnan , Malcolm J. Bevan
发明人： Husam N. Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy A. Chancellor , Anand Krishnan , Malcolm J. Bevan
IPC分类号： H01L21/31 , H01L21/469 , H01L21/8234
CPC分类号： H01L21/02326 , H01L21/0214 , H01L21/02337 , H01L21/265 , H01L21/28202 , H01L21/3144 , H01L21/823857 , H01L29/518 , H01L29/7833
摘要： A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
摘要翻译：一种降低在温度和电压应力之后导致的MOSFET晶体管的阈值电压偏移的方法，以及根据该方法制造的集成电路器件。该方法包括以下步骤：在半导体衬底上形成氮化介电层，并将氮化介电层在低压下进行退火。

6. 发明授权

US07514308B2 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers 有权
标题翻译： CMOS器件在NMOS栅极电介质层和PMOS栅极电介质层中具有不同量的氮
公开(公告)号：US07514308B2
公开(公告)日：2009-04-07
申请号：US11745930
申请日：2007-05-08
申请人： Ajith Varghese , Husam N. Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam N. Alshareef , Rajesh Khamankar
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

7. 发明授权

US07339240B2 Dual-gate integrated circuit semiconductor device 有权
标题翻译：双栅集成电路半导体器件
公开(公告)号：US07339240B2
公开(公告)日：2008-03-04
申请号：US11343680
申请日：2006-01-31
申请人： Brian K. Kirkpatrick , Rajesh Khamankar , Malcolm J. Bevan , April Gurba , Husam N. Alshareef , Clinton L. Montgomery , Mark H. Somervell
发明人： Brian K. Kirkpatrick , Rajesh Khamankar , Malcolm J. Bevan , April Gurba , Husam N. Alshareef , Clinton L. Montgomery , Mark H. Somervell
IPC分类号： H01L29/76
CPC分类号： H01L21/823462 , H01L21/28202 , H01L21/31111 , H01L21/31138 , H01L21/3144 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L29/518
摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.
摘要翻译：本发明提供一种制造双栅极半导体器件的方法。一方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高电压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化叶片在暴露的氮化高压栅极介电层上的促进剂残留物。该方法还包括将暴露的氮化高压电介质经受等离子体去除促进剂残留物。

8. 发明授权

US07049242B2 Post high voltage gate dielectric pattern plasma surface treatment 有权
标题翻译：后高压栅介质图案等离子体表面处理
公开(公告)号：US07049242B2
公开(公告)日：2006-05-23
申请号：US10752886
申请日：2004-01-06
申请人： Brian K. Kirkpatrick , Rajesh Khamankar , Malcolm J. Bevan , April Gurba , Husam N. Alshareef , Clinton L. Montgomery , Mark H. Somervell
发明人： Brian K. Kirkpatrick , Rajesh Khamankar , Malcolm J. Bevan , April Gurba , Husam N. Alshareef , Clinton L. Montgomery , Mark H. Somervell
IPC分类号： H01L21/302
CPC分类号： H01L21/823462 , H01L21/28202 , H01L21/31111 , H01L21/31138 , H01L21/3144 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L29/518
摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.
摘要翻译：本发明提供一种制造双栅极半导体器件的方法。一方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高电压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化叶片在暴露的氮化高压栅极介电层上的促进剂残留物。该方法还包括将暴露的氮化高压电介质经受等离子体去除促进剂残留物。

9. 发明授权

US09177806B2 System and method for mitigating oxide growth in a gate dielectric 有权
标题翻译：用于减轻栅极电介质中的氧化物生长的系统和方法
公开(公告)号：US09177806B2
公开(公告)日：2015-11-03
申请号：US13017828
申请日：2011-01-31
申请人： Malcolm J. Bevan , Haowen Bu , Hiroaki Niimi , Husam N. Alshareef
发明人： Malcolm J. Bevan , Haowen Bu , Hiroaki Niimi , Husam N. Alshareef
IPC分类号： H01J37/00 , H01L21/00 , H01L21/28 , H01L21/316 , H01L21/318 , H01L29/51 , H01L29/78 , H01L29/49
CPC分类号： H01L21/28158 , C23C16/45557 , C23C16/4582 , H01J37/32752 , H01J37/32825 , H01J37/32899 , H01J2237/3321 , H01L21/02181 , H01L21/0223 , H01L21/02255 , H01L21/02318 , H01L21/02323 , H01L21/02326 , H01L21/02329 , H01L21/02332 , H01L21/0234 , H01L21/28035 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3105 , H01L21/31604 , H01L21/318 , H01L21/3205 , H01L21/324 , H01L21/67161 , H01L21/67167 , H01L21/67196 , H01L21/67201 , H01L21/6776 , H01L29/42364 , H01L29/4908 , H01L29/4916 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/78
摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
摘要翻译：可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

10. 发明申请

US20110120374A1 System and Method for Mitigating Oxide Growth in a Gate Dielectric 审中-公开
标题翻译：降低栅极电介质中氧化物生长的系统和方法
公开(公告)号：US20110120374A1
公开(公告)日：2011-05-26
申请号：US13017828
申请日：2011-01-31
申请人： Malcolm J. Bevan , Haowen Bu , Hiroaki Niimi , Husam N. Alshareef
发明人： Malcolm J. Bevan , Haowen Bu , Hiroaki Niimi , Husam N. Alshareef
IPC分类号： H01L21/469
CPC分类号： H01L21/28158 , C23C16/45557 , C23C16/4582 , H01J37/32752 , H01J37/32825 , H01J37/32899 , H01J2237/3321 , H01L21/02181 , H01L21/0223 , H01L21/02255 , H01L21/02318 , H01L21/02323 , H01L21/02326 , H01L21/02329 , H01L21/02332 , H01L21/0234 , H01L21/28035 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3105 , H01L21/31604 , H01L21/318 , H01L21/3205 , H01L21/324 , H01L21/67161 , H01L21/67167 , H01L21/67196 , H01L21/67201 , H01L21/6776 , H01L29/42364 , H01L29/4908 , H01L29/4916 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/78
摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
摘要翻译：可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式