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41. 发明授权

US07960238B2 Multiple indium implant methods and devices and integrated circuits therefrom 有权
标题翻译：多种铟注入方法和装置以及集成电路
公开(公告)号：US07960238B2
公开(公告)日：2011-06-14
申请号：US12344843
申请日：2008-12-29
申请人： Puneet Kohli , Manoj Mehrotra
发明人： Puneet Kohli , Manoj Mehrotra
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/823412 , H01L29/1083 , H01L29/66507 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm−3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface. A method to form an IC including at least one NMOS transistor includes implanting a first In implant at a first energy and a second In implant at a second energy, wherein the first In implant together with the second In implant form an In region having a retrograde profile under at least a portion of the channel region, and wherein the second energy is at least 5 keV more than the first energy.
摘要翻译：集成电路（IC）包括至少一个NMOS晶体管，其中NMOS晶体管包括具有半导体表面的衬底，以及形成在栅极电介质上的包括栅电极的表面中或其上的栅堆叠，其中沟道区域位于在栅极电介质下方的半导体表面。源极和漏极区域在栅极堆叠的相对侧上。具有逆行轮廓的An In区域在通道区域的至少一部分的下方。逆行曲线包括（i）与栅极电介质的半导体表面界面处的表面In浓度小于5×10 16 cm -3，（ii）从栅极电介质下方的半导体表面至少20nm的峰In浓度，并且其中（iii）峰In浓度比半导体表面界面处的In浓度高至少两（2）个数量级。一种形成包括至少一个NMOS晶体管的IC的方法，包括以第二能量以第一能量和第二In的植入物注入第一InNo，其中第一In植入物与第二In植入物一起形成具有逆行的In区域在所述通道区域的至少一部分下形成，并且其中所述第二能量比所述第一能量多至少5keV。

42. 发明授权

US07691700B2 Multi-stage implant to improve device characteristics 有权
标题翻译：多级植入物以改善装置特性
公开(公告)号：US07691700B2
公开(公告)日：2010-04-06
申请号：US11769058
申请日：2007-06-27
申请人： Manoj Mehrotra , Stan Ashburn , Shaoping Tang
发明人： Manoj Mehrotra , Stan Ashburn , Shaoping Tang
IPC分类号： H01L21/8238
CPC分类号： G11C11/412 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L27/11 , H01L27/1104 , H01L29/1083 , H01L29/7833
摘要： One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.
摘要翻译：本发明人的概念的一个方面涉及形成半导体器件的方法。在该方法中，在半导体本体上形成栅极结构。源极/漏极掩模在半导体本体注入源上形成图案，并且形成与栅极结构相关联的漏极区。在形成植入的源区和漏区之后，在包括至少两个植入物的源极和漏极区域上执行多级注入，其中第一注入的剂量和能量与第二植入物的剂量和能量不同。还公开了其它方法和装置。

43. 发明授权

US07611939B2 Semiconductor device manufactured using a laminated stress layer 有权
标题翻译：使用层压应力层制造的半导体器件
公开(公告)号：US07611939B2
公开(公告)日：2009-11-03
申请号：US11745044
申请日：2007-05-07
申请人： Manoj Mehrotra , Antonio L. P. Rotondaro , Puneet Kohli
发明人： Manoj Mehrotra , Antonio L. P. Rotondaro , Puneet Kohli
IPC分类号： H01L21/8238
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76828 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.
摘要翻译：提出了形成半导体器件的方法。该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底之上形成层压应力层。层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。

44. 发明申请

US20090184348A1 Slim Spacer Implementation to Improve Drive Current 审中-公开
标题翻译：提高驱动电流的Slim Spacer实现
公开(公告)号：US20090184348A1
公开(公告)日：2009-07-23
申请号：US12372868
申请日：2009-02-18
申请人： Manoj Mehrotra , Karen Hildegard Ralston Kirmse , Shirin Siddiqui
发明人： Manoj Mehrotra , Karen Hildegard Ralston Kirmse , Shirin Siddiqui
IPC分类号： H01L29/78
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/6653 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.
摘要翻译：半导体衬垫在晶体管制造中实现。更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

45. 发明授权

US07524777B2 Method for manufacturing an isolation structure using an energy beam treatment 有权
标题翻译：使用能量束处理制造隔离结构的方法
公开(公告)号：US07524777B2
公开(公告)日：2009-04-28
申请号：US11610758
申请日：2006-12-14
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/00
CPC分类号： H01L21/3105 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.
摘要翻译：本发明提供一种制造半导体器件的方法。用于制造半导体器件的方法尤其可以包括在衬底的开口内形成一层或多层材料，所述开口和所述一层或多层形成隔离结构的至少一部分，并使至少一层的能量束处理，所述能量束处理被配置为改变受其影响的一个或多个层的应力，从而改变衬底中的应力。

46. 发明申请

US20090090990A1 FORMATION OF NITROGEN CONTAINING DIELECTRIC LAYERS HAVING AN IMPROVED NITROGEN DISTRIBUTION 有权
标题翻译：形成具有改进的氮分布的含氮电介质层
公开(公告)号：US20090090990A1
公开(公告)日：2009-04-09
申请号：US11856310
申请日：2007-10-09
申请人： Hiroaki Niimi , Manoj Mehrotra
发明人： Hiroaki Niimi , Manoj Mehrotra
IPC分类号： H01L21/31 , H01L27/00
CPC分类号： H01L21/823462 , H01L21/2822 , H01L21/3144 , H01L21/3185 , H01L21/3211 , H01L29/518 , H01L29/78
摘要： Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.
摘要翻译：提供了一种制造栅极电介质的方法。该方法，但不限于，包括使硅衬底经受第一等离子体氮化处理以在其中引入氮区域。该方法还包括使用含氮氧化剂气体在氮区域上生长电介质材料层，并对电介质材料层进行第二等离子体氮化处理，从而在氮区域上形成氮化介电材料层。

47. 发明授权

US07510923B2 Slim spacer implementation to improve drive current 有权
标题翻译：改进间隔实现来提高驱动电流
公开(公告)号：US07510923B2
公开(公告)日：2009-03-31
申请号：US11641578
申请日：2006-12-19
申请人： Manoj Mehrotra , Karen Hildegard Ralston Kirmse , Shirin Siddiqui
发明人： Manoj Mehrotra , Karen Hildegard Ralston Kirmse , Shirin Siddiqui
IPC分类号： H01L21/338
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/6653 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.
摘要翻译：半导体衬垫在晶体管制造中实现。更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

48. 发明申请

US20080076225A1 METHOD FOR MANUFACTURING A GATE SIDEWALL SPACER USING AN ENERGY BEAM TREATMENT 有权
标题翻译：使用能量束处理方法制造闸门间隔板的方法
公开(公告)号：US20080076225A1
公开(公告)日：2008-03-27
申请号：US11533798
申请日：2006-09-21
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其他步骤之外，用于制造半导体器件的方法可以包括在衬底上形成栅极结构，形成靠近栅极结构的侧壁的栅极侧壁间隔的至少一部分，以及使栅极侧壁间隔物的至少一部分能量束处理被配置为改变栅极侧壁间隔物的至少一部分的应力，从而改变其下的衬底中的应力。

49. 发明申请

US20050042831A1 Dual salicide process for optimum performance 有权
标题翻译：双重自杀过程，以获得最佳性能
公开(公告)号：US20050042831A1
公开(公告)日：2005-02-24
申请号：US10643341
申请日：2003-08-19
申请人： Manoj Mehrotra
发明人： Manoj Mehrotra
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： The present invention pertains to forming respective suicides on multiple transistors in a single process. High performance is facilitated with simple and highly integrated process flows. As such, transistors, and an integrated circuit containing the transistors, can be fabricated efficiently and at a low cost. The different suicides can be formed with different materials and/or to different thicknesses. As such, the silicides can have different electrical characteristics, such as resistivity and conductivity. These different attributes instill the transistors with different work functions when formed as gate contacts thereon. This provides an integrated circuit containing the transistors with diverse operating capabilities allowing for the execution of operations requiring more flexibility and/or functionality.
摘要翻译：本发明涉及在单个过程中在多个晶体管上形成相应的自杀剂。通过简单高度集成的流程可以实现高性能。因此，可以以低成本有效地制造晶体管和包含晶体管的集成电路。不同的自杀可以用不同的材料和/或不同的厚度形成。因此，硅化物可以具有不同的电特性，例如电阻率和电导率。这些不同的属性在其上形成为栅极接触时，灌注具有不同功函数的晶体管。这提供了包含具有不同操作能力的晶体管的集成电路，允许执行需要更多灵活性和/或功能的操作。

50. 发明授权

US06677208B2 Transistor with bottomwall/sidewall junction capacitance reduction region and method 有权
标题翻译：具有底壁/侧壁结电容降低区域的晶体管及方法
公开(公告)号：US06677208B2
公开(公告)日：2004-01-13
申请号：US10253827
申请日：2002-09-24
申请人： Manoj Mehrotra , Kaiping Liu
发明人： Manoj Mehrotra , Kaiping Liu
IPC分类号： H01L21336
CPC分类号： H01L29/1083 , H01L21/266 , H01L29/66492
摘要： A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using the gate structure as a mask, wherein a channel is defined in the substrate between the source region and the drain region. A bottomwall/sidewall junction capacitance reduction region extending within and between the source region and the drain region is formed, wherein the bottomwall/sidewall junction capacitance reduction region extends at least partially through the bottomwall junction or the sidewall junction.
摘要翻译：制造晶体管的方法包括在半导体衬底的外部形成栅极结构，其中栅极结构包括栅极，栅极绝缘体和侧壁，并且使用栅极结构作为掩模在衬底中形成源极区域和漏极区域，其中，在源极区域和漏极区域之间的衬底中限定沟道。形成在源极区域和漏极区域内部和之间延伸的底壁/侧壁结电容减小区域，其中底壁/侧壁接合电容减小区域至少部分延伸穿过底壁结或侧壁连接处。

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