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41. 发明申请

US20070153741A1 Seamless roaming across wireless subnets using source address forwarding 有权
标题翻译：使用源地址转发无缝地漫游无线子网
公开(公告)号：US20070153741A1
公开(公告)日：2007-07-05
申请号：US11646904
申请日：2006-12-28
申请人： Richard Blanchette , Martin Bouchard , Anil Gupta , Yannick Koehler , Gilbert Moineau , Frederic Mouveaux , Roger Sands , Pierre Trudeau
发明人： Richard Blanchette , Martin Bouchard , Anil Gupta , Yannick Koehler , Gilbert Moineau , Frederic Mouveaux , Roger Sands , Pierre Trudeau
IPC分类号： H04Q7/00
CPC分类号： H04W8/02 , H04L45/66 , H04W40/36 , H04W80/02 , H04W80/04
摘要： To enable devices to detect L3 roaming users and to take appropriate forwarding actions, L3 knowledge is introduced inside a bridge in a non-intrusive way. In particular, as a client moves from a subnet associated with a first network element to a subnet associated with a second network element, a determination is made regarding whether the client is roaming. This is done by evaluating a source IP address within a L3 packet header within a first frame received at the second network element. If, as a result of the evaluating step, it is determined that the client is roaming, an L2 bridge forwarding table in the second network element is configured to include a source MAC address of the client together with information identifying at least a destination interface for use in directing client data traffic back towards the subnet associated with the first network element. The first frame is then forwarded. In one embodiment, the traffic is directed back towards the subnet associated with the first network element via a GRE encapsulation tunnel, although any convenient tunneling mechanism can be used. According to another feature, given information cached at the foreign access point is used to enable the roaming client to continue to seamlessly receive inbound traffic prior to or during the configuration of the L2 bridge forwarding table (i.e., before any outbound traffic is actually sent from the client).
摘要翻译：为了使设备能够检测L3漫游用户并采取适当的转发动作，L3桥梁内部以非侵入式方式引入知识。特别地，当客户端从与第一网络元件相关联的子网移动到与第二网络元件相关联的子网时，确定客户端是否正在漫游。这是通过评估在第二网络单元接收的第一帧内的L3分组报头内的源IP地址来完成的。如果作为评估步骤的结果，确定客户端正在漫游，则第二网元中的L2桥转发表被配置为将客户端的源MAC地址与至少标识至少目的地接口的信息用于将客户端数据业务引导回与第一网络元件相关联的子网。然后转发第一帧。在一个实施例中，尽管可以使用任何方便的隧道机制，但是业务通过GRE封装隧道被引导回到与第一网络元件相关联的子网。根据另一特征，在外部接入点处缓存的给定信息被用于使得漫游客户端能够在配置L2网桥转发表之前或期间继续无缝地接收入站流量（即，在任何出站流量实际上从客户端）。

42. 发明申请

US20050114589A1 Wear leveling techniques for flash EEPROM systems 失效
公开(公告)号：US20050114589A1
公开(公告)日：2005-05-26
申请号：US11028882
申请日：2005-01-03
申请人： Karl Lofgren , Robert Norman , Gregory Thelin , Anil Gupta
发明人： Karl Lofgren , Robert Norman , Gregory Thelin , Anil Gupta
IPC分类号： G11C8/12 , G11C16/34 , G06F12/00
CPC分类号： G11C16/3495 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C8/12 , G11C16/349
摘要： A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

43. 发明授权

US06615296B2 Efficient implementation of first-in-first-out memories for multi-processor systems 有权
标题翻译：高效地实现多处理器系统的先进先出存储器
公开(公告)号：US06615296B2
公开(公告)日：2003-09-02
申请号：US09881512
申请日：2001-06-14
申请人： Thomas Daniel , Anil Gupta
发明人： Thomas Daniel , Anil Gupta
IPC分类号： G06F1320
CPC分类号： G06F15/167
摘要： To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.
摘要翻译：为了减少跨处理器系统中的系统总线的FIFO访问周期，在多处理器系统中，两个处理器通过FIFO通过系统总线进行通信，则提供两个独立的FIFO描述符。第一描述符由位于板上的处理器由FIFO维护，第二描述符由通过总线与FIFO通信的板外处理器来维护。当一个处理器执行FIFO操作时，处理器通过总线上的存储器访问来更新其他处理器的描述符。此外，一个模块向另一个模块传递信用以指示后者具有连续执行多个FIFO操作的许可。在一个实施例中，使用特殊的非有效数据值来指示空的FIFO位置。

44. 发明授权

US06359810B1 Page mode erase in a flash memory array 有权
标题翻译：页面模式在闪存阵列中擦除
公开(公告)号：US06359810B1
公开(公告)日：2002-03-19
申请号：US09542434
申请日：2000-04-04
申请人： Anil Gupta , Steven J. Schumann
发明人： Anil Gupta , Steven J. Schumann
IPC分类号： G11C1604
CPC分类号： G11C5/147 , G11C16/16
摘要： In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential of approximately −10 Volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row or rows.
摘要翻译：在闪存阵列的扇区中，提供了PAGE ERASE和MULTIPLE PAGE ERASE操作模式。在PAGE ERASE和MULTIPLE PAGE ERASE操作模式下，将大约-10伏特的优选隧道电位施加到被选择用于擦除的行或行上的闪存单元的栅极，并且连接到闪存单元被驱动到大约6.5伏的优选电压。为了减少存储器单元在非所选择的行或行以外的行中的非预期擦除，将大约1至2伏特的优选偏置电压施加到除所选择的行或行之外的行中的所有快闪存储器单元的栅极。

45. 发明授权

US06317812B1 Device and method for controlling solid-state memory system 失效
标题翻译：用于控制固态存储器系统的装置和方法
公开(公告)号：US06317812B1
公开(公告)日：2001-11-13
申请号：US09657369
申请日：2000-09-08
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G06F1200
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件阵列，其经由具有极少线路的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。序列化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个内存设备都由阵列装载分配一个阵列地址。通过在设备总线上广播的适当地址来选择存储设备，而不需要通常的专用选择信号。保留阵列安装配置用于无条件地选择安装的设备。通过设备总线广播的保留地址将取消所有先前选择的存储设备。通过读取流技术增强读取性能，其中当当前大量数据被序列化并从存储器子系统移出到控制器模块时，控制器模块还设置下一个数据块的地址以开始寻址内存系统。

46. 发明授权

US06148363A Device and method for controlling solid-state memory system 失效
公开(公告)号：US06148363A
公开(公告)日：2000-11-14
申请号：US64528
申请日：1998-04-21
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G06F3/06 , G06F12/06 , G06F13/16 , G06F13/42 , G11C5/00 , G11C5/06 , G11C8/12 , G06F12/00
CPC分类号： G11C5/04 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G11C5/00 , G11C5/066 , G11C8/12 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

47. 发明授权

US5987258A Register reservation method for fast context switching in microprocessors 失效
标题翻译：微处理器快速上下文切换的注册预约方法
公开(公告)号：US5987258A
公开(公告)日：1999-11-16
申请号：US883137
申请日：1997-06-27
申请人： Thomas Daniel , Anil Gupta
发明人： Thomas Daniel , Anil Gupta
IPC分类号： G06F9/46 , G06F9/45
CPC分类号： G06F9/462
摘要： Microprocessor main programs and their interrupt handling routines are written in a high level programming language such as C. Each is compiled separately, and each is compiled invoking a compiler option which commands the compiler to not use a given set of registers in the compiled code. Post-processing is then performed on the compiled interrupt code to replace accesses to a first set of registers with accesses to the given set of registers. The result is that while both the main program and the interrupt handler were written in C, the compiled code for each employs different registers. This allows context switching from the main program to the interrupt handler and back again with almost none of the overhead traditionally associated with context switching register save and restore operations during exception handling.
摘要翻译：微处理器主程序及其中断处理例程以高级编程语言（如C）编写。每个编译单独编译，每个编译调用编译器选项，命令编译器在编译代码中不使用给定的一组寄存器。然后对编译的中断代码进行后处理，以通过访问给定的寄存器组来替换对第一组寄存器的访问。结果是当主程序和中断处理程序都用C编写时，每个编译代码使用不同的寄存器。这允许从主程序到中断处理程序的上下文切换，并且在异常处理期间几乎没有传统上与上下文切换寄存器保存和恢复操作相关联的开销。

48. 发明授权

US5822245A Dual buffer flash memory architecture with multiple operating modes 失效
公开(公告)号：US5822245A
公开(公告)日：1998-10-13
申请号：US824175
申请日：1997-03-26
申请人： Anil Gupta , Steven J. Schumann
发明人： Anil Gupta , Steven J. Schumann
IPC分类号： G11C7/10 , G11C16/10 , G11C16/26 , G11C11/34
CPC分类号： G11C7/1045 , G11C16/10 , G11C16/26 , G11C16/3431
摘要： A flash memory array architecture comprising a flash memory array, first and second memory buffer, and I/O interface circuit which has several operating modes which permit data to be read from the flash memory array, several operating modes which permit data to be programmed into the flash memory array, and a mode for rewriting the data in the flash memory array.In the four read modes, one of the pages stored in the flash memory array is read, the data stored in either of first or second memory buffers is read, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers, the data in one of the pages of data stored in the flash memory array is read and then compared to the data read from either of first or second memory buffers. In the four write modes, data from an input stream is written into a selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array, data in either of first or second memory buffers is written into a previously erased page in the flash memory array, and data from an input stream is written into the selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array. In the auto page rewrite mode, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers. The data stored in the page of the flash memory array just read is erased, and then in the same cycle, the page of data stored in the selected first or second memory buffer is written into the erased page in the flash memory array.

49. 发明授权

US5815024A Look-up table using multi-level decode 失效
公开(公告)号：US5815024A
公开(公告)日：1998-09-29
申请号：US833363
申请日：1997-04-04
申请人： Srinivas T. Reddy , Anil Gupta
发明人： Srinivas T. Reddy , Anil Gupta
IPC分类号： H03K17/00 , H03K17/693 , H03K17/62
CPC分类号： H03K17/005 , H03K17/693
摘要： A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

50. 发明授权

US5548551A Negative voltage decoding in non-volatile memories 失效
标题翻译：在非易失性存储器中进行负电压解码
公开(公告)号：US5548551A
公开(公告)日：1996-08-20
申请号：US409779
申请日：1995-03-24
申请人： Chi-Ming Wang , Anil Gupta , Hiten D. S. Randhawa
发明人： Chi-Ming Wang , Anil Gupta , Hiten D. S. Randhawa
IPC分类号： G11C16/08 , G11C16/30 , G11C7/00
CPC分类号： G11C16/30 , G11C16/08
摘要： A negative voltage decoder applies a negative voltage to the sense line of a selected row of a memory array but not to sense lines of unselected rows. The negative voltage decoder includes a negative voltage source, an array of P-channel transistors, and a negative voltage address signal generator. P-channel transistors in the array have gates coupled to address lines, so that address signals on the address lines turn on the P-channel transistors and connect only the selected sense line to the negative voltage source. A negative voltage charge pumps in the negative voltage address signal generator generates address signals lower than the negative voltage source. In one embodiment, the transistor array has rows of P-channel transistors which fit the pitch of the memory array and individual P-channel transistors which are stacked laterally away from the memory array, and each row of P-channel transistors couples through a set of individual transistor to a set of sense lines. When a positive voltage decoder applies a positive voltage to the sense lines, the negative voltage address signal generator provides a high voltage to shut off the transistors directly coupled to the sense lines. An isolation circuit isolates the positive voltage row decoder from the negative voltage applied by the negative voltage decoder.
摘要翻译：负电压解码器将负电压施加到存储器阵列的选定行的感测线，但不检测未选行的行。负电压解码器包括负电压源，P沟道晶体管阵列和负电压地址信号发生器。阵列中的P沟道晶体管具有耦合到地址线的栅极，使得地址线上的地址信号导通P沟道晶体管，并且仅将所选择的检测线连接到负电压源。负电压地址信号发生器中的负电压电荷泵产生低于负电压源的地址信号。在一个实施例中，晶体管阵列具有排列的P沟道晶体管，其配合存储器阵列的间距和从存储器阵列横向堆叠的各个P沟道晶体管，并且每行P沟道晶体管通过一组的单个晶体管到一组感测线。当正电压解码器向感测线施加正电压时，负电压地址信号发生器提供高电压以截止直接耦合到感测线的晶体管。隔离电路将正电压行解码器与由负电压解码器施加的负电压隔离。

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