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41. 发明授权

US06933205B2 Integrated circuit device and method of manufacturing the same 失效
标题翻译：集成电路装置及其制造方法
公开(公告)号：US06933205B2
公开(公告)日：2005-08-23
申请号：US10298059
申请日：2002-11-18
申请人： Mie Matsuo , Nobuo Hayasaka , Noriaki Matsunaga , Katsuya Okumura
发明人： Mie Matsuo , Nobuo Hayasaka , Noriaki Matsunaga , Katsuya Okumura
IPC分类号： H01F41/04 , H01F17/00 , H01L21/822 , H01L23/48 , H01L23/522 , H01L23/64 , H01L27/04 , H01L27/08 , H01L21/76
CPC分类号： H01L23/645 , H01L23/481 , H01L23/5227 , H01L27/08 , H01L2224/05009 , H01L2224/05027 , H01L2224/05155 , H01L2224/05169 , H01L2224/05171 , H01L2224/05568 , H01L2224/056 , H01L2224/05647 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/13091 , Y10S438/957 , H01L2924/00 , H01L2924/00014
摘要： The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 μm, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.
摘要翻译：本发明提供了一种集成电路，包括半导体衬底，形成在半导体衬底的一个主表面侧的有源元件，通过将绝缘材料埋入半导体衬底的主表面侧而形成的绝缘区域具有至少20μm的深度的凹槽，以及直接或间接形成在绝缘区域上的无源元件。无源元件最好是一个电感器。

42. 发明授权

US06784680B2 Contact probe with guide unit and fabrication method thereof 失效
标题翻译：带导向单元的接触式探头及其制造方法
公开(公告)号：US06784680B2
公开(公告)日：2004-08-31
申请号：US10445181
申请日：2003-05-23
申请人： Tsuyoshi Haga , Katsuya Okumura , Nobuo Hayasaka , Hideki Shibata , Noriaki Matsunaga
发明人： Tsuyoshi Haga , Katsuya Okumura , Nobuo Hayasaka , Hideki Shibata , Noriaki Matsunaga
IPC分类号： G01R3102
CPC分类号： G01R1/06716 , G01R1/06722 , G01R1/06733 , G01R1/06738
摘要： A contact probe is fabricated by a method including a lithography step and a plating step. The contact probe includes a plunger unit to form contact with a circuit to be tested, a spring unit, and a lead wire connection unit, all formed integrally so as to have a three dimensional configuration with uniform thickness with respect to a predetermined plane configuration in a thickness direction perpendicular to the predetermined plane configuration. Preferably, a guide unit parallel to the spring unit is also formed integrally. Further preferably, the contact probe is formed integrally also including a stopper for each unitary configuration of the spring unit constituted by a leaf spring.
摘要翻译：通过包括光刻步骤和电镀步骤的方法制造接触探针。接触探针包括与被测试电路形成接触的柱塞单元，弹簧单元和引线连接单元，其全部形成为具有相对于预定平面构造具有均匀厚度的三维构造垂直于预定平面构造的厚度方向。优选地，与弹簧单元平行的引导单元也整体形成。进一步优选地，接触探针一体地形成，还包括用于由板簧构成的弹簧单元的每个单一构造的止动件。

43. 发明授权

US06504227B1 Passive semiconductor device mounted as daughter chip on active semiconductor device 失效
标题翻译：被动半导体器件作为子芯片安装在有源半导体器件上
公开(公告)号：US06504227B1
公开(公告)日：2003-01-07
申请号：US09605433
申请日：2000-06-29
申请人： Mie Matsuo , Nobuo Hayasaka , Noriaki Matsunaga , Katsuya Okumura
发明人： Mie Matsuo , Nobuo Hayasaka , Noriaki Matsunaga , Katsuya Okumura
IPC分类号： H01L2900
CPC分类号： H01L23/645 , H01L23/481 , H01L23/5227 , H01L27/08 , H01L2224/05009 , H01L2224/05027 , H01L2224/05155 , H01L2224/05169 , H01L2224/05171 , H01L2224/05568 , H01L2224/056 , H01L2224/05647 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/13091 , Y10S438/957 , H01L2924/00 , H01L2924/00014
摘要： The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &mgr;m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.
摘要翻译：本发明提供了一种集成电路，包括半导体衬底，形成在半导体衬底的一个主表面侧的有源元件，通过将绝缘材料埋入半导体衬底的主表面侧而形成的绝缘区域具有至少20μm的深度的凹槽，以及直接或间接形成在绝缘区域上的无源元件。无源元件最好是一个电感器。

44. 发明授权

US06375545B1 Chemical mechanical method of polishing wafer surfaces 有权
标题翻译：抛光晶圆表面的化学机械方法
公开(公告)号：US06375545B1
公开(公告)日：2002-04-23
申请号：US09484252
申请日：2000-01-18
申请人： Hiroyuki Yano , Gaku Minamihaba , Yukiteru Matsui , Nobuo Hayasaka , Katsuya Okumura , Akira Iio , Masayuki Hattori , Masayuki Motonari
发明人： Hiroyuki Yano , Gaku Minamihaba , Yukiteru Matsui , Nobuo Hayasaka , Katsuya Okumura , Akira Iio , Masayuki Hattori , Masayuki Motonari
IPC分类号： B24B100
CPC分类号： H01L21/3212 , C09G1/02 , C09K3/1463 , H01L21/31053 , Y10S977/775 , Y10S977/888
摘要： It is an object of the present invention to provide an aqueous dispersion and CMP slurry that can achieve polishing at an adequate rate without producing scratches in the polishing surfaces of wafer working films, and a polishing process for wafer surfaces and a process for manufacture of a semiconductor device using them. A CMP slurry and the like of the present invention contains polymer particles with a crosslinked structure and a mean particle size of 0.13-0.8 &mgr;m. The CMP slurry may contain no surfactant, and may contain the surfactant of not greater than 0.15 wt %. A CMP slurry and the like of another present invention contains polymer particles and inorganic particles of silica, aluminum and the like. A mean particle size of the polymer particles may be not greater than a mean particle size of the inorganic particles. And the mean particle size of the inorganic coagulated particles may be 0.1-1.0 &mgr;m, and may be smaller than the mean particle size of the polymer particles. The CMP slurry is used as a polishing agent and a working film of a silicon oxide film, an aluminum film, a tungsten film or a copper film formed on a wafer is polished. And a semiconductor device is manufactured by using the CMP slurry.
摘要翻译：本发明的目的是提供一种水分散体和CMP浆料，其可以以足够的速率实现抛光，而不会在晶片工作薄膜的抛光表面中产生划痕，以及用于晶片表面的抛光工艺和制造半导体器件使用它们。本发明的CMP浆料等含有交联结构，平均粒径为0.13〜0.8μm的聚合物粒子。 CMP浆料可以不含表面活性剂，并且可以含有不大于0.15重量％的表面活性剂。另一个本发明的CMP浆料等含有聚合物颗粒和二氧化硅，铝等的无机颗粒。聚合物颗粒的平均粒径可以不大于无机颗粒的平均粒度。无机凝结粒子的平均粒径可以为0.1〜1.0μm，并且可以小于聚合物粒子的平均粒径。将CMP浆料用作抛光剂，并且研磨在晶片上形成的氧化硅膜，铝膜，钨膜或铜膜的工作膜。并且通过使用CMP浆料制造半导体器件。

45. 发明授权

US06239495B1 Multichip semiconductor device and memory card 失效
标题翻译：多芯片半导体器件和存储卡
公开(公告)号：US06239495B1
公开(公告)日：2001-05-29
申请号：US09363031
申请日：1999-07-29
申请人： Koji Sakui , Junichi Miyamoto , Nobuo Hayasaka , Katsuya Okumura
发明人： Koji Sakui , Junichi Miyamoto , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L2348
CPC分类号： G11C5/06 , G11C5/04 , G11C8/12 , H01L23/481 , H01L25/0657 , H01L2224/05567 , H01L2224/05573 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599
摘要： A multichip semiconductor device comprises a plurality of semiconductor chips, each including elements integrated in a semiconductor substrate. The semiconductor chips have substantially the same structure. Each semiconductor chip includes a connecting plug inserted in a through hole made through the semiconductor substrate. The semiconductor chips are stacked in layers. The connecting plugs of the semiconductor chips are selectively connected through metal bumps. Allocation of addresses of the semiconductor chips is designated by a connecting pattern of the bumps.
摘要翻译：多芯片半导体器件包括多个半导体芯片，每个半导体芯片包括集成在半导体衬底中的元件。半导体芯片具有基本上相同的结构。每个半导体芯片包括插入通过半导体衬底制成的通孔中的连接插头。半导体芯片层叠。通过金属凸块选择性地连接半导体芯片的连接插头。半导体芯片的地址分配由凸块的连接图案表示。

46. 发明授权

US07387717B2 Method of performing electrolytic treatment on a conductive layer of a substrate 失效
标题翻译：在基板的导电层上进行电解处理的方法
公开(公告)号：US07387717B2
公开(公告)日：2008-06-17
申请号：US10631726
申请日：2003-08-01
申请人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
发明人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
IPC分类号： C25D7/12
CPC分类号： H01L21/6719 , C25D7/123 , C25D17/001 , C25D17/12 , C25D17/14 , H01L21/2885 , H01L21/67046 , H01L21/67051 , H01L21/6708 , H01L21/6715 , H01L21/6723 , H01L21/76877 , H01L21/76879 , H01L2924/0002 , H05K3/423 , H01L2924/00
摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
摘要翻译：用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。密封材料90接触表面的周缘部分，以水密的方式密封该部分。阴极电极88在与基板接触时通过电流。阴极部38与基板保持部36一体地旋转。电极臂部30在阴极部38的上方，水平且垂直地移动，阳极98面朝下。将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。因此，电镀处理和附带的处理可以通过单个单元进行。

47. 发明申请

US20050124164A1 Fine particle film forming apparatus and method and semiconductor device and manufacturing method for the same 审中-公开
标题翻译：微粒成膜装置及其制造方法及半导体装置及其制造方法
公开(公告)号：US20050124164A1
公开(公告)日：2005-06-09
申请号：US11033871
申请日：2005-01-13
申请人： Atsuko Sakata , Keiichi Sasaki , Nobuo Hayasaka , Katsuya Okumura , Hirotaka Nishino
发明人： Atsuko Sakata , Keiichi Sasaki , Nobuo Hayasaka , Katsuya Okumura , Hirotaka Nishino
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/485 , H01L21/302 , H01L21/461
CPC分类号： H01L24/03 , H01L23/481 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/742 , H01L2224/0401 , H01L2224/05022 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/11001 , H01L2224/1131 , H01L2224/11334 , H01L2224/1147 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13144 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01028 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/0105 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 μm or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.
摘要翻译：在焊盘电极上形成阻挡膜之后，在阻挡膜上选择性地沉积直径为2μm以下的Ni粒子，形成Ni微粒膜。然后，通过Ni微粒膜在焊盘电极上设置由焊料球形成的突起电极。此后，通过热处理使凸块电极熔融，将Ni微粒膜与凸点电极接合。因此，凸块电极结构完成。

48. 发明授权

US06846750B1 High precision pattern forming method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的高精度图案形成方法
公开(公告)号：US06846750B1
公开(公告)日：2005-01-25
申请号：US09604724
申请日：2000-06-28
申请人： Tokuhisa Ohiwa , Shoji Seta , Nobuo Hayasaka , Katsuya Okumura , Akihiro Kojima , Junko Ohuchi , Tsukasa Azuma , Hideo Ichinose , Ichiro Mizushima
发明人： Tokuhisa Ohiwa , Shoji Seta , Nobuo Hayasaka , Katsuya Okumura , Akihiro Kojima , Junko Ohuchi , Tsukasa Azuma , Hideo Ichinose , Ichiro Mizushima
IPC分类号： H01L21/302 , H01L21/033 , H01L21/30 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/316 , H01L21/768 , H01L21/461
CPC分类号： H01L21/76802 , H01L21/0331 , H01L21/31111 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/76816 , H01L21/7682
摘要： According to the present invention, there is provided a method of manufacturing a semiconductor device, where a soluble thin film which is soluble in a dissolving liquid is used. According to the method of the present invention, when a soluble thin film is formed between a film to be processed which should be patterned and a mask pattern, it becomes possible to remove the mask pattern by lifting-off. On the other hand, when the thin film is used for a dummy layer for forming an air wiring structure, the dummy layer can be removed without performing ashing using oxygen plasma.
摘要翻译：根据本发明，提供一种制造半导体器件的方法，其中使用可溶于溶解液的可溶性薄膜。根据本发明的方法，当在要被图案化的被处理膜和掩模图案之间形成可溶性薄膜时，可以通过剥离来去除掩模图案。另一方面，当薄膜用于形成空气布线结构的虚拟层时，可以去除虚拟层而不用氧等离子体进行灰化。

49. 发明授权

US06809421B1 Multichip semiconductor device, chip therefor and method of formation thereof 失效
标题翻译：多芯片半导体器件，芯片及其形成方法
公开(公告)号：US06809421B1
公开(公告)日：2004-10-26
申请号：US09377486
申请日：1999-08-20
申请人： Nobuo Hayasaka , Katsuya Okumura , Keiichi Sasaki , Mie Matsuo
发明人： Nobuo Hayasaka , Katsuya Okumura , Keiichi Sasaki , Mie Matsuo
IPC分类号： H01L2348
CPC分类号： H01L23/642 , H01L21/76898 , H01L23/367 , H01L23/481 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/00
摘要： A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
摘要翻译：公开了一种多芯片半导体器件，其中堆叠芯片，每个芯片包括形成在顶部的半导体衬底和电路部件，以及形成在半导体衬底的顶部上的层间绝缘膜。至少一个芯片具有穿过半导体衬底和层间绝缘膜的通孔中形成的金属的连接插头。具有连接插头的芯片通过该连接插头与另一个芯片电连接。

50. 发明授权

US06538323B1 Semiconductor device having an electrode structure comprising a conductive fine particle film 失效
标题翻译：具有包含导电性微粒膜的电极结构的半导体装置
公开(公告)号：US06538323B1
公开(公告)日：2003-03-25
申请号：US09449941
申请日：1999-11-29
申请人： Atsuko Sakata , Keiichi Sasaki , Nobuo Hayasaka , Katsuya Okumura , Hirotaka Nishino
发明人： Atsuko Sakata , Keiichi Sasaki , Nobuo Hayasaka , Katsuya Okumura , Hirotaka Nishino
IPC分类号： H01L2348
CPC分类号： H01L24/03 , H01L23/481 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/742 , H01L2224/0401 , H01L2224/05022 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/11001 , H01L2224/1131 , H01L2224/11334 , H01L2224/1147 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13144 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01028 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/0105 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 &mgr;m or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.
摘要翻译：在焊盘电极上形成阻挡膜之后，在阻挡膜上选择性地沉积直径为2μm以下的Ni粒子，形成Ni微粒膜。然后，通过Ni微粒膜在焊盘电极上设置由焊料球形成的突起电极。此后，通过热处理使凸块电极熔融，将Ni微粒膜与凸点电极接合。因此，凸块电极结构完成。

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