专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07981732B2 Programming of laser fuse 有权
标题翻译：激光保险丝编程
公开(公告)号：US07981732B2
公开(公告)日：2011-07-19
申请号：US12105366
申请日：2008-04-18
申请人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
发明人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
IPC分类号： H01L21/268
CPC分类号： H01L23/5258 , H01L23/525 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.
摘要翻译：激光熔丝编程方法。激光熔丝具有包括具有在暴露于激光束之后改变其电阻的特性的材料的熔断体。激光束被引导到熔丝链，激光束被控制，使得响应于激光束对熔丝链的冲击，熔丝链的电阻改变，但是熔丝链不会被吹掉。

42. 发明授权

US07892926B2 Fuse link structures using film stress for programming and methods of manufacture 有权
标题翻译：使用膜应力的熔断器连接结构进行编程和制造方法
公开(公告)号：US07892926B2
公开(公告)日：2011-02-22
申请号：US12508962
申请日：2009-07-24
申请人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
发明人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
IPC分类号： H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.
摘要翻译：形成可编程熔丝结构的方法包括在衬底中形成至少一个浅沟槽隔离（STI），在至少一个STI上形成e-熔丝，并在该电熔丝上沉积层间电介质（ILD）层。另外，该方法包括移除电子熔丝下的至少一个STI的至少一部分以在e熔丝的一部分下方提供空气间隙，并将e-fuse上的ILD层的至少一部分移除到在电子熔断器的部分上方提供气隙。

43. 发明申请

US20100290264A1 OPTOELECTRONIC MEMORY DEVICES 有权
标题翻译：光电存储器件
公开(公告)号：US20100290264A1
公开(公告)日：2010-11-18
申请号：US12842158
申请日：2010-07-23
申请人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
发明人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
IPC分类号： G11C13/04 , G11C11/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.
摘要翻译：一个结构。该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

44. 发明申请

US20090230555A1 TUNGSTEN LINER FOR ALUMINUM-BASED ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE 审中-公开
标题翻译：基于铝的电阻互连结构的TUNGSTEN LINER
公开(公告)号：US20090230555A1
公开(公告)日：2009-09-17
申请号：US12049698
申请日：2008-03-17
申请人： Jonathan D. Chapple-Sokol , Daniel A. Delibac , Zhong-Xiang He , Tom C. Lee , William J. Murphy , Timothy D. Sullivan , David C. Thomas , Daniel S. Vanslette
发明人： Jonathan D. Chapple-Sokol , Daniel A. Delibac , Zhong-Xiang He , Tom C. Lee , William J. Murphy , Timothy D. Sullivan , David C. Thomas , Daniel S. Vanslette
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53223 , H01L23/5329 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.
摘要翻译：在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。一种金属层堆叠，包括从底部到顶部的低氧反应性金属层，底部过渡金属层，底部过渡金属氮化物层，铝 - 铜层，任选的顶部过渡金属层和顶部过渡层金属氮化物层。金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和电介质材料层之间的化合物的形成，因此提高了至少一种铝基金属线的电迁移率不与介电材料层相互作用。

45. 发明申请

US20090183131A1 STRUCTURE FOR SEMICONDUCTOR ON-CHIP REPAIR SCHEME FOR NEGATIVE BIAS TEMPERATURE INSTABILITY 有权
标题翻译：半导体芯片修复方案结构的负偏差温度不稳定性
公开(公告)号：US20090183131A1
公开(公告)日：2009-07-16
申请号：US12050990
申请日：2008-03-19
申请人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
发明人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L23/345 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.
摘要翻译：公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。修理方案在每个设备上使用加热元件。加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

46. 发明申请

US20080297188A1 IC CHIP STRESS TESTING 失效
标题翻译： IC芯片应力测试
公开(公告)号：US20080297188A1
公开(公告)日：2008-12-04
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

47. 发明申请

US20080231312A1 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US20080231312A1
公开(公告)日：2008-09-25
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

48. 发明申请

US20080194064A1 PROGRAMMING OF LASER FUSE 有权
标题翻译：激光熔丝的编程
公开(公告)号：US20080194064A1
公开(公告)日：2008-08-14
申请号：US12105366
申请日：2008-04-18
申请人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
发明人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
IPC分类号： H01L21/268
CPC分类号： H01L23/5258 , H01L23/525 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.
摘要翻译：激光熔丝编程方法。激光熔丝具有包括具有在暴露于激光束之后改变其电阻的特性的材料的熔断体。激光束被引导到熔丝链，激光束被控制，使得响应于激光束对熔丝链的冲击，熔丝链的电阻改变，但是熔丝链不会被吹掉。

49. 发明授权

US07166913B2 Heat dissipation for heat generating element of semiconductor device and related method 有权
标题翻译：半导体器件发热元件的散热及相关方法
公开(公告)号：US07166913B2
公开(公告)日：2007-01-23
申请号：US10907873
申请日：2005-04-19
申请人： Anil K. Chinthakindi , Lawrence A. Clevenger , Tom C. Lee , Gerald Matusiewicz , Conal E. Murray , Chih-Chao Yang
发明人： Anil K. Chinthakindi , Lawrence A. Clevenger , Tom C. Lee , Gerald Matusiewicz , Conal E. Murray , Chih-Chao Yang
IPC分类号： H01L23/34
CPC分类号： H01L23/5228 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.
摘要翻译：公开了相对于半导体器件中的发热元件的散热的结构和方法。该结构包括多个与发热元件垂直一致的传热线，以及从每个传热线到半导体器件的基板的至少一个互连路径。在一个实施例中，发热元件包括非第一金属水平的电阻器。本发明与传统的BEOL互连方案兼容，使得从电阻器到周围互连布线的传热量最小化，从而消除了布线中的载流能力的损失。

50. 发明授权

US08822993B2 Integrated circuit including sensor structure, related method and design structure 有权
标题翻译：集成电路包括传感器结构，相关方法和设计结构
公开(公告)号：US08822993B2
公开(公告)日：2014-09-02
申请号：US13550813
申请日：2012-07-17
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee
IPC分类号： H01L23/58 , H01L21/66 , H01L23/48 , G01R31/28
CPC分类号： H01L22/34 , G01R31/2858 , H01L22/30 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，集成电路包括：基板; 第一金属层，设置在所述基板上并且包括被构造为指示所述集成电路的一部分中的裂纹的传感器结构; 以及设置在所述第一金属层附近的第二金属层，所述第二金属层包括靠近所述传感器结构设置的导线部件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式