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41. 发明授权

US5946268A Internal clock signal generation circuit including delay line, and synchronous type semiconductor memory device including internal clock signal 失效
标题翻译：内部时钟信号发生电路包括延迟线，同步型半导体存储器件包括内部时钟信号
公开(公告)号：US5946268A
公开(公告)日：1999-08-31
申请号：US012558
申请日：1998-01-23
申请人： Hisashi Iwamoto , Yasumitsu Murai
发明人： Hisashi Iwamoto , Yasumitsu Murai
IPC分类号： G11C11/407 , G06F1/06 , G11C7/22 , G11C11/4076 , H03K5/00 , H03K5/13 , H03L7/00 , G11C7/00
CPC分类号： G11C7/22 , H03K5/133 , H03K2005/00071
摘要： An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.
摘要翻译：内部时钟生成电路包括多个逆变器电路串联连接的延迟线。开关和电容器连接到每个逆变器电路的输出节点。连接到每个逆变器电路的开关根据相应的控制信号单独打开/关闭。响应于开关导通，相应的逆变器电路的输出节点和电容器被连接，从而相应的逆变器电路的输出节点的电容被改变。结果，信号的传输速率被改变。

42. 发明授权

US5881017A Synchronous semiconductor memory device allowing fast operation in either of prefetch operation and full page mode operation 失效
标题翻译：同步半导体存储器件允许在预取操作和全页模式操作中快速操作
公开(公告)号：US5881017A
公开(公告)日：1999-03-09
申请号：US992901
申请日：1997-12-18
申请人： Junko Matsumoto , Hisashi Iwamoto
发明人： Junko Matsumoto , Hisashi Iwamoto
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1021 , G11C7/1072
摘要： SDRAM 1000 outputs data, in a 2-bit prefetch operation, by simultaneously selecting two columns in memory cell array banks A0 and A1 in accordance with column select signals YE0-YEk and YO0-YOk issued from Y-address operation circuit 68. In a full page mode, data are output from all columns crossing rows alternately selected in memory cell array banks A0 and A1 in accordance with an internal address signal issued from a Y-address counter circuit 82.
摘要翻译： SDRAM1000通过根据从Y地址运算电路68发出的列选择信号YE0-YEk和YO0-YOk同时选择存储单元阵列组A0和A1中的两列来输出2位预取操作中的数据。在全页模式，根据从Y地址计数器电路82发出的内部地址信号，从存储单元阵列组A0和A1中交替选择的行的所有列输出数据。

43. 发明授权

US09135966B2 Semiconductor device including memory capable of reducing power consumption 有权
标题翻译：包括能够降低功耗的存储器的半导体装置
公开(公告)号：US09135966B2
公开(公告)日：2015-09-15
申请号：US13566779
申请日：2012-08-03
申请人： Hisashi Iwamoto , Yuji Yano , Kazunari Inoue
发明人： Hisashi Iwamoto , Yuji Yano , Kazunari Inoue
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1096 , G11C7/222
摘要： A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.
摘要翻译：半导体器件包括多个存储器阵列和多个存储器阵列控制电路。多个存储器阵列控制电路中的每一个包括用于控制存储器阵列的读/写操作的读/写控制电路，以及用于基于时钟信号和来自该存储器阵列控制电路的输出信号选择和激活存储器阵列的选择电路读/写控制电路。

44. 发明授权

US06338113B1 Memory module system having multiple memory modules 有权
标题翻译：具有多个存储器模块的存储器模块系统
公开(公告)号：US06338113B1
公开(公告)日：2002-01-08
申请号：US09195037
申请日：1998-11-19
申请人： Takashi Kubo , Kenichi Yasuda , Hisashi Iwamoto
发明人： Takashi Kubo , Kenichi Yasuda , Hisashi Iwamoto
IPC分类号： G06F1202
CPC分类号： G06F13/1684
摘要： There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an input/output terminal, a logic chip, and a plurality of switch transistors each connected between a corresponding internal data bus and a corresponding input/output terminal to turn on/off in response to a control signal from the logic chip. The plurality of switch transistors in a memory module selected by the memory controller are turned on, and the plurality of switch transistors in the memory modules other than the selected memory module are turned off. Thus, the capacity of the memory modules may be increased while maintaining high-speed data transfer.
摘要翻译：提供了存储器控制器，多个存储器模块和多个存储器模块公共的外部数据总线。多个存储器模块各自包括多个存储器芯片，连接在对应的存储器芯片和输入/输出端子之间的多个内部数据总线，逻辑芯片和多个开关晶体管，每个开关晶体管连接在相应的内部数据总线以及相应的输入/输出端子，以响应于来自逻辑芯片的控制信号而导通/截止。由存储器控制器选择的存储器模块中的多个开关晶体管导通，并且除了选择的存储器模块之外的存储器模块中的多个开关晶体管截止。因此，可以在保持高速数据传输的同时增加存储器模块的容量。

45. 发明授权

US6052329A Output circuit and synchronous semiconductor memory device having a function of preventing output of invalid data 失效
标题翻译：具有防止无效数据输出功能的输出电路和同步半导体存储器件
公开(公告)号：US6052329A
公开(公告)日：2000-04-18
申请号：US120031
申请日：1998-07-21
申请人： Aiko Nishino , Hisashi Iwamoto
发明人： Aiko Nishino , Hisashi Iwamoto
IPC分类号： G11C11/409 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1072
摘要： An output circuit and a synchronous semiconductor memory device according to the invention suppress output of invalid data, and perform data output with exact timings. The synchronous semiconductor memory device includes a plurality of output buffers provided correspondingly to data I/O terminals, a plurality of data transfer latch circuits and a plurality of output control signal latch circuits. Data transfer latch circuit transfers data read from a memory cell to the corresponding output buffer in response to an internal clock signal. The output control signal latch circuit issues an output control signal to the corresponding output buffer in synchronization with the internal clock signal. Thereby, an output timing of each output buffer can be controlled independently of the other output buffer.
摘要翻译：根据本发明的输出电路和同步半导体存储器件抑制无效数据的输出，并以精确的定时执行数据输出。同步半导体存储器件包括与数据I / O端子相对应设置的多个输出缓冲器，多个数据传输锁存电路和多个输出控制信号锁存电路。数据传输锁存电路响应于内部时钟信号将从存储器单元读取的数据传送到相应的输出缓冲器。输出控制信号锁存电路与内部时钟信号同步地向对应的输出缓冲器发出输出控制信号。因此，可以独立于另一个输出缓冲器来控制每个输出缓冲器的输出定时。

46. 发明授权

US5892730A Synchronous semiconductor memory device operable in a plurality of data write operation modes 失效
标题翻译：在多个数据写入操作模式下可操作的同步半导体存储器件
公开(公告)号：US5892730A
公开(公告)日：1999-04-06
申请号：US980963
申请日：1997-12-01
申请人： Nobuyuki Sato , Hisashi Iwamoto
发明人： Nobuyuki Sato , Hisashi Iwamoto
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1039 , G11C7/1072
摘要： A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating circuit is set to either the pipelined mode or the prefetch mode. A mode switching circuit merely switches reset timings of a write buffer in accordance with a CAS latency. Therefore, the internal data write mode can be easily switched in accordance with an operation environment, and the synchronous semiconductor memory device can implement multiple data write modes with one chip.
摘要翻译：同步半导体存储器件可以使用一个芯片实现流水线模式和预取模式中的任一种。根据存储在模式寄存器中的CAS（列地址选通）等待时间4指令信号MCL4，将来自控制信号发生电路的控制信号的生成序列设置为流水线模式或预取模式。模式切换电路仅根据CAS延迟来切换写缓冲器的复位定时。因此，可以根据操作环境容易地切换内部数据写入模式，并且同步半导体存储器件可以利用一个芯片实现多个数据写入模式。

47. 发明授权

US5521463A Cathode ray tube having a cancel coil for earth magnetism 失效
标题翻译：具有用于地磁的取消线圈的阴极射线管
公开(公告)号：US5521463A
公开(公告)日：1996-05-28
申请号：US511319
申请日：1995-08-04
申请人： Junichi Ogawa , Satoru Nakanishi , Hisashi Iwamoto , Kenji Ebe
发明人： Junichi Ogawa , Satoru Nakanishi , Hisashi Iwamoto , Kenji Ebe
IPC分类号： H04N9/29 , H01J29/00 , H01J29/76
CPC分类号： H01J29/003 , H04N9/29 , H01J2229/003 , H01J2229/0053
摘要： Image rotation of a cathode ray tube caused by the influence of earth magnetism can be suppressed. An image rotation correcting coil for generating a magnetic field of the direction opposite to that of a horizontal earth magnetism component of the direction vertical to the picture tube is disposed between a deflection yoke formed at the outside of a tube envelope of a cathode ray tube and an anode button.
摘要翻译：可以抑制由地磁的影响引起的阴极射线管的图像旋转。用于产生与垂直于显像管的方向的水平地磁部件的方向相反方向的磁场的图像旋转校正线圈设置在形成于阴极射线管的管壳外侧的偏转线圈和阳极按钮。

48. 发明授权

US5019953A High voltage generator for television receiver 失效
标题翻译：电视接收机高压发生器
公开(公告)号：US5019953A
公开(公告)日：1991-05-28
申请号：US483861
申请日：1990-02-23
申请人： Seiji Kawaberi , Hisashi Iwamoto
发明人： Seiji Kawaberi , Hisashi Iwamoto
IPC分类号： H04N3/18 , H04N3/185
CPC分类号： H04N3/185
摘要： A high voltage generator using a flyback transformer to generate high voltage pulses and including a control switching transistor inserted in a power supply circuit in a manner to be turned off during a trace interval. The amount of electric energy accumulated in a resonance circuit is intermittently controlled by the on-off action of such switching transistor, so that the level of the high pulse voltage outputted via the transformer can be maintained constant to consequently enhance the response characteristic in the voltage regulation while minimizing the number of required component elements.
摘要翻译：一种利用回扫变压器产生高电压脉冲的高压发生器，并且包括在跟踪间隔期间以断开方式插入电源电路中的控制开关晶体管。通过这种开关晶体管的通断动作间歇地控制在谐振电路中累积的电能量，使得经由变压器输出的高电压电压的电平可以保持恒定，从而提高电压的响应特性同时最小化所需组分元素的数量。

49. 发明授权

US08625360B2 Semiconductor storage device operative to search for data 有权
标题翻译：用于搜索数据的半导体存储设备
公开(公告)号：US08625360B2
公开(公告)日：2014-01-07
申请号：US13165457
申请日：2011-06-21
申请人： Hisashi Iwamoto , Yuji Yano , Koji Yamamoto
发明人： Hisashi Iwamoto , Yuji Yano , Koji Yamamoto
IPC分类号： G11C7/10
CPC分类号： G11C15/04
摘要： To provide a semiconductor storage device capable of performing a search of the next data while performing a search of certain data. A first comparator compares data output to a bit line from a memory cell with first search data by activating a word line. A second comparator compares data output to a bit line from the memory cell with second search data by activating a word line. Data output to a bit line by the activation of one word line is input to both the first comparator and second comparator.
摘要翻译：提供能够在执行某些数据的搜索的同时对下一个数据进行搜索的半导体存储装置。第一比较器通过激活字线将来自存储器单元的数据输出与第一搜索数据进行比较。第二比较器通过激活字线将来自存储器单元的数据输出与第二搜索数据进行比较。通过一个字线的激活将数据输出到位线被输入到第一比较器和第二比较器。

50. 发明授权

US06489823B2 Semiconductor device capable of generating highly precise internal clock 失效
公开(公告)号：US06489823B2
公开(公告)日：2002-12-03
申请号：US09809298
申请日：2001-03-16
申请人： Hisashi Iwamoto
发明人： Hisashi Iwamoto
IPC分类号： H03L706
CPC分类号： G11C7/222 , G11C7/1072 , H03L7/0814 , H03L7/0818 , H03L7/089 , H03L7/0997
摘要： A DLL circuit includes a delay line having a configuration with delay stages receiving alternate complementary clock signals ECK and /ECK having an adjusted phase difference therebetween. A capacitor can be used to adjust the phase difference between signals ECK and /ECK to allow the delay line to provide an amount of delay varying minutely. Preferably, for a fast clock, delay adjustment starts with a shift register having an initial value providing an intermediate amount of delay, and for a slow clock, delay adjustment starts with the shift register having an initial value providing a minimal amount of delay. There can be provided a semiconductor device provided with a DLL circuit accommodating a fast clock with reduced jitter.

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