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41. 发明授权

US5388230A Parallel processor having multi-processing units either connected or bypassed in either series or parallel by the use of bus switching 失效
标题翻译：具有多处理单元的并行处理器通过使用总线切换以串联或并联方式连接或旁路
公开(公告)号：US5388230A
公开(公告)日：1995-02-07
申请号：US104945
申请日：1993-08-12
申请人： Hiromichi Yamada , Koyo Katsura
发明人： Hiromichi Yamada , Koyo Katsura
IPC分类号： G06F13/40 , G06F15/173 , G06F15/80 , G06T1/20 , G06F13/00
CPC分类号： G06F13/4022 , G06F15/17343
摘要： A parallel process which includes a plurality of processing units connected to each other via input/output ports. Each of the plurality of processing units includes a memory for storing a program and data, a local bus for inputting/outputting the program and data to and from the memory having an address signal line, a data signal line, and a control signal line, a CPU for reading the program from the memory via the local bus, reading data needed to execute the program from the memory via the local bus, and storing data which has been updated due to the execution of the program in the memory via the local bus, and a plurality of input/output ports for connecting the local bus to a plurality of outside buses. The input/output ports are used by the CPU to input/output data to and from an outside memory connected to an outside bus or by an outside CPU, connected to an outside bus, to input/output data to and from the memory. At least one bypass switch is provided for controllably connecting two of the outside buses to permit data transference between the outside CPU and the outside memory thereby bypassing the CPU and the memory. Also provided is a main CPU for setting program and data in the processing units and recovering data from the processing units.
摘要翻译：并行处理，其包括经由输入/输出端口彼此连接的多个处理单元。多个处理单元中的每一个包括用于存储程序和数据的存储器，用于向具有地址信号线，数据信号线和控制信号线的存储器输入/输出程序和数据的本地总线，经由本地总线从存储器读取程序的CPU，经由本地总线读取从存储器执行程序所需的数据，以及经由本地总线将由于执行程序而被更新的数据存储在存储器中的CPU 以及用于将本地总线连接到多个外部总线的多个输入/输出端口。输入/输出端口被CPU用于向连接到外部总线的外部存储器或连接到外部总线的外部CPU输入/输出数据，以从存储器输入/输出数据。提供至少一个旁路开关用于可控地连接两个外部总线以允许外部CPU和外部存储器之间的数据传输，从而绕过CPU和存储器。还提供了用于在处理单元中设置程序和数据并从处理单元恢复数据的主CPU。

42. 发明授权

US5177401A Phosphor and cathode-ray tube using the same 失效
标题翻译：磷光体和阴极射线管使用相同
公开(公告)号：US5177401A
公开(公告)日：1993-01-05
申请号：US444961
申请日：1989-12-04
申请人： Hidetsugu Matsukiyo , Teruki Suzuki , Hajime Yamamoto , Yasuhiko Uehara , Yasukazu Morita , Yoshihiro Koseki , Hiromichi Yamada , Shigeo Fujino , Takashi Hase , Tsutomu Yamada , Susumu Omatoi
发明人： Hidetsugu Matsukiyo , Teruki Suzuki , Hajime Yamamoto , Yasuhiko Uehara , Yasukazu Morita , Yoshihiro Koseki , Hiromichi Yamada , Shigeo Fujino , Takashi Hase , Tsutomu Yamada , Susumu Omatoi
IPC分类号： C09K11/77 , C09K11/80 , H01J29/20
CPC分类号： C09K11/7792 , C09K11/7774 , H01J29/20
摘要： Disclosed are terbium-activated oxide phosphors having incorporated, at least one of ytterbium, thulium, samarium and europium. Incorporation of the element (s) has made it possible to produce phosphors exhibiting high brightness and suffering little brightness deterioration under high-density electron bombardment.
摘要翻译：公开了掺入了镱，ium，钐和铕中的至少一种的铽活化氧化物荧光体。元件的结合使得可以生产在高密度电子轰击下表现出高亮度并且几乎没有亮度劣化的荧光体。

43. 发明授权

US4492869A Radiation detector 失效
标题翻译：辐射检测器
公开(公告)号：US4492869A
公开(公告)日：1985-01-08
申请号：US313171
申请日：1981-10-20
申请人： Atsushi Suzuki , Hiromichi Yamada , Yoko Uchida , Hideki Kohno , Minoru Yoshida
发明人： Atsushi Suzuki , Hiromichi Yamada , Yoko Uchida , Hideki Kohno , Minoru Yoshida
IPC分类号： A61B6/00 , G01T1/164 , G01T1/20
CPC分类号： G01T1/2002 , G01T1/2018
摘要： In a radiation detector having a radiation-stimulated light emitting scintillator and a photodetector for receiving the light emission from the scintillator, the scintillator is formed of a layer of phosphor particles and a light scattering layer is provided in an optical path between the phosphor particle layer and the photodetector. Light generated in the surface of the scintillator is scattered and absorbed by the light scattering layer in some degree so that the reduced quantity of light incident upon the photodetector lowers the output of the photodetector. This effect is balanced with the lowering of the photodetector output due to the absorption and scattering of light generated at the inner parts of the scintillator and further removes anisotropic light emission. As a result, signal-to-noise ratio is greatly improved.A shielding layer between the scintillator and photodetector prevents secondary radiation such as scattered and fluorescent radiation from reaching the photodetector. The shielding layer can also serve as the scattering layer.
摘要翻译：在具有辐射激发的发光闪烁体的辐射检测器和用于接收来自闪烁体的发光的光检测器中，闪烁体由荧光体颗粒层形成，并且光散射层设置在荧光体颗粒层和光电检测器。在闪烁器表面产生的光在一定程度上被光散射层散射和吸收，使得入射到光电检测器上的光的减少使得光电检测器的输出降低。由于在闪烁器的内部部分产生的光的吸收和散射，光电检测器输出的降低会使这种效果平衡，并进一步消除各向异性发光。结果，信噪比大大提高。闪烁体和光电检测器之间的屏蔽层防止二次辐射如散射和荧光辐射到达光电探测器。屏蔽层也可以用作散射层。

44. 发明授权

US4442360A Radiation detector 失效
标题翻译：辐射检测器
公开(公告)号：US4442360A
公开(公告)日：1984-04-10
申请号：US257426
申请日：1981-04-24
申请人： Atsushi Suzuki , Hiromichi Yamada , Yoko Uchida , Hideki Kohno , Fukino Tadashi , Minoru Yoshida
发明人： Atsushi Suzuki , Hiromichi Yamada , Yoko Uchida , Hideki Kohno , Fukino Tadashi , Minoru Yoshida
IPC分类号： C09K11/00 , C09K11/08 , C09K11/84 , G01T1/20 , G01T1/202 , G01J1/58
CPC分类号： G01T1/2023 , G01T1/2002
摘要： A radiation detector comprising a scintillator exhibiting luminescence by the action of radioactive rays and a light detector detecting light output of said scintillator, characterized in that said scintillator is a phosphor represented by the formula:(A.sub.1-x-y Ln.sub.x Ce.sub.y).sub.2 O.sub.2 S:Xwherein A is at least one element selected from the group consisting of Y, La and Gd; Ln is at least one element selected from the group consisting of Pr, Tb and Eu; and X is at least one element selected from the group consisting of F, Cl and Br; and the values of x and y are 0.000003.gtoreq.x.gtoreq.0.2, and 0.000001.gtoreq.y.gtoreq.0.005, and the amount of X is 0 to 1000 ppm on weight basis, has a very short after glow time because of having Ce in the phosphor.
摘要翻译：一种辐射检测器，包括通过放射线的作用产生发光的闪烁体和检测所述闪烁体的光输出的光检测器，其特征在于，所述闪烁体是由下式表示的荧光体：（A1-x-yLnxCey）2O2S：X其中A 是选自Y，La和Gd中的至少一种元素; Ln是选自Pr，Tb和Eu中的至少一种元素; X为至少一种选自F，Cl和Br的元素; x和y的值为0.000003> = => = 0.000001> / = y> / = 0.005，X为0〜1000ppm的重量，在辉光时间后非常短因为在磷光体中有Ce。

45. 发明授权

US07890233B2 Microcontroller, control system and design method of microcontroller 失效
公开(公告)号：US07890233B2
公开(公告)日：2011-02-15
申请号：US12388861
申请日：2009-02-19
申请人： Hiromichi Yamada , Nobuyasu Kanekawa , Teruaki Sakata
发明人： Hiromichi Yamada , Nobuyasu Kanekawa , Teruaki Sakata
IPC分类号： G06F17/00 , G06F17/50 , G06F1/04 , G06F11/00
CPC分类号： G06F11/1641 , G06F11/1679 , Y02T10/82
摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.

46. 发明授权

US07765269B2 Communications system, and information processing device and control device incorporating said communications system 失效
标题翻译：通信系统，以及包含所述通信系统的信息处理设备和控制设备
公开(公告)号：US07765269B2
公开(公告)日：2010-07-27
申请号：US10980837
申请日：2004-11-04
申请人： Nobuyasu Kanekawa , Hiromichi Yamada , Kohei Sakurai , Kotaro Shimamura , Yuichiro Morita , Satoshi Tanaka
发明人： Nobuyasu Kanekawa , Hiromichi Yamada , Kohei Sakurai , Kotaro Shimamura , Yuichiro Morita , Satoshi Tanaka
IPC分类号： G06F15/16
CPC分类号： G06F13/4217
摘要： This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.
摘要翻译：本发明提供了能够在利用现有技术的简单性的同时进行广播的通信系统，并且还提供并入通信系统的控制设备和信息处理系统。在本发明中，芯片选择信号被提供用于独立地传输（TXCSi）和接收（RXCSi）以及如现有技术中的各个芯片。也就是说，指示从节点是否被选择作为向主节点发送信号的节点和通信方向的一组信号从主节点输出到从节点。

47. 发明授权

US07752527B2 Microcontroller and RAM 失效
标题翻译：微控制器和RAM
公开(公告)号：US07752527B2
公开(公告)日：2010-07-06
申请号：US11604806
申请日：2006-11-28
申请人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
发明人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
IPC分类号： G11C29/00
CPC分类号： G06F11/167 , G06F11/08 , G06F11/183
摘要： A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
摘要翻译：提供了一种微控制器，其中硬件的增加被抑制，并且可以提高对RAM的软件错误的数据校正能力。执行根据程序的处理的微控制器包括CPU和RAM，用于存储由CPU处理的数据，其中在RAM中定义复用区域，并且当这些区域被访问时，访问由CPU输出的地址和执行通过向CPU输出的地址添加或减去某个值而获得的地址的复制访问。通过这种方式，可以将相同的数据存储在多个区域中，并且可以提高可靠性。

48. 发明申请

US20090249271A1 MICROCONTROLLER, CONTROL SYSTEM AND DESIGN METHOD OF MICROCONTROLLER 失效
标题翻译：微控制器，微控制器的控制系统和设计方法
公开(公告)号：US20090249271A1
公开(公告)日：2009-10-01
申请号：US12388861
申请日：2009-02-19
申请人： Hiromichi Yamada , Nobuyasu Kanekawa , Teruaki Sakata
发明人： Hiromichi Yamada , Nobuyasu Kanekawa , Teruaki Sakata
IPC分类号： G06F17/50 , G06F1/12
CPC分类号： G06F11/1641 , G06F11/1679 , Y02T10/82
摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
摘要翻译：提供具有相同功能的两个数据处理单元，其中一个用于主机，另一个用于比较，电机单元的控制由主机执行，主数据处理单元和电路单元同步操作利用第一时钟信号，第二数据处理单元与具有与第一时钟信号相同的周期和不同相位的第二时钟信号同步地操作，并且在比较电路中比较两个数据处理单元的处理结果。触发器设置在从电路单元到比较数据处理单元和从主数据处理单元到比较器的信号路径的信号路径上，并且第一和第二时钟信号都用于触发器的锁存时钟根据其输入信号。

49. 发明授权

US07245248B2 A/D converter and a microcontroller including the same 有权
标题翻译： A / D转换器和包含它的微控制器
公开(公告)号：US07245248B2
公开(公告)日：2007-07-17
申请号：US10912542
申请日：2004-08-06
申请人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
发明人： Yuichiro Morita , Kohei Sakurai , Nobuyasu Kanekawa , Masatoshi Hoshino , Hiromichi Yamada , Kotaro Shimamura , Satoshi Tanaka , Naoki Yada
IPC分类号： H03M1/12
CPC分类号： H03M1/1225
摘要： In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.
摘要翻译：在A / D转换器和包含该A / D转换器的微控制器中，对于每个A / D转换，模拟输入通道的选择模式的数量增加，并且使用仅具有基本功能的A / D转换器进行A / D转换，而不施加加载到CPU上 A / D转换器或DMA传输装置包括包括一个或多个条目的A / D转换表。每个条目包括用于设置是否对各个模拟输入通道执行A / D转换的使能位以及用于设置A / D转换执行次数的多个计数号位。

50. 发明授权

US06830446B2 Clamping apparatus 有权
标题翻译：夹紧装置
公开(公告)号：US06830446B2
公开(公告)日：2004-12-14
申请号：US10264354
申请日：2002-10-04
申请人： Hiroyoshi Harada , Itaru Matsuo , Takehiko Ikegami , Hiromichi Yamada , Jyunji Sakakibara , Hiroaki Tanoue
发明人： Hiroyoshi Harada , Itaru Matsuo , Takehiko Ikegami , Hiromichi Yamada , Jyunji Sakakibara , Hiroaki Tanoue
IPC分类号： B29C4566
CPC分类号： B29C45/661
摘要： A clamping apparatus includes upper and lower platens; one or more tiebars connecting the platens; and an intermediate platen between the upper and lower platens for movement relative to and along the tiebars. Upper and lower mold halves are provided on the upper and intermediate platens, respectively. A linkage connects the lower and intermediate platens. The linkage includes upper and lower links connected with each other for rotation on an intermediate shaft. The upper and lower links are pivotably supported on first and second shafts fixed to the intermediate and lower platens, repectively. The intermediate shaft is operatively connected with a drive mechanism so that the drive mechanism transmits a driving force to the linkage, and the lower platen is moved relative to the intermediate platen. A set of a radical needle bearing and a thrust bearing is used for at least one of the intermediate, first, and second shafts.
摘要翻译：夹紧装置包括上压板和下压板; 连接压板的一个或多个连杆; 以及在上压板和下压板之间的中间压板，用于相对于并沿着拉杆运动。上半模和下半模分别设置在上压板和中压板上。连杆连接下部和中间压板。联动装置包括彼此连接以在中间轴上旋转的上部和下部连杆。上连杆和下连杆分别可枢转地支撑在固定到中间和下压板上的第一和第二轴上。中间轴与驱动机构可操作地连接，使得驱动机构向联动装置传递驱动力，下压板相对于中间压板移动。一组自由基滚针轴承和推力轴承用于中间轴，第一轴和第二轴中的至少一个轴。

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