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1. 发明授权

US06463520B1 Processor for executing instruction codes of two different lengths and device for inputting the instruction codes 失效
标题翻译：用于执行两种不同长度的指令代码的处理器和用于输入指令代码的装置
公开(公告)号：US06463520B1
公开(公告)日：2002-10-08
申请号：US08811005
申请日：1997-03-04
申请人： Sugako Otani , Shunichi Iwata
发明人： Sugako Otani , Shunichi Iwata
IPC分类号： G06E1500
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30149 , G06F9/30152 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/322
摘要： Exemplary embodiments of the present invention are directed toward a technique which facilitates the process instruction codes in processor. According to the present invention, a memory device is provided which comprises a plurality of 2N-bit word boundaries, where N is greater than or equal to one. The processor of the present invention executes instruction codes of a 2N-bit length and a N-bit length. The instruction codes are stored in the memory device is such a way that the 2-N bit word boundaries contains either a single 2N-bit instruction code or two N-bit instruction codes. The most significant bit of each instruction code serves as a instruction format identifier which controls the execution (or decoding) sequence of the instruction codes. As a result, only two transfer paths from an instruction fetch portion to an instruction decode portion of the processor are necessary thereby reducing the hardware requirement of the processor and increasing system throughput.
摘要翻译：本发明的示例性实施例涉及促进处理器中的处理指令代码的技术。根据本发明，提供一种包括多个2N位字边界的存储器件，其中N大于或等于1。本发明的处理器执行2N位长度和N位长度的指令代码。指令码存储在存储器件中，使得2-N位字边界包含单个2N位指令代码或两个N位指令代码。每个指令代码的最高有效位用作控制指令代码的执行（或解码）序列的指令格式标识符。结果，仅需要从处理器的指令提取部分到指令解码部分的两个传送路径，从而减少处理器的硬件需求并提高系统吞吐量。

2. 发明授权

US06209079B1 Processor for executing instruction codes of two different lengths and device for inputting the instruction codes 有权
标题翻译：用于执行两种不同长度的指令代码的处理器和用于输入指令代码的装置
公开(公告)号：US06209079B1
公开(公告)日：2001-03-27
申请号：US09562643
申请日：2000-05-01
申请人： Sugako Otani , Shunichi Iwata
发明人： Sugako Otani , Shunichi Iwata
IPC分类号： G06F930
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30149 , G06F9/30152 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/322
摘要： For a processor having instruction codes of two instruction lengths (16 bits and 32 bits), methods of locating the instruction codes are limited to two types: (1) two 16-bit instruction codes are stored within 32-bit word boundaries, and (2) a single 32-bit instruction code is stored intactly within the 32-bit word boundaries. A branch destination address is specified only on the 32-bit word boundary. The MSB of each instruction code serves as a 1-bit instruction length identifier for controlling the execution sequence of the instruction codes. This provides two transfer paths from an instruction fetch portion to an instruction decode portion within the processor, achieving reduction in code side and in the amount of hardware and, accordingly, the increase in operating speed.
摘要翻译：对于具有两个指令长度（16位和32位）的指令代码的处理器，定位指令代码的方法被限制为两种类型：（1）两个16位指令代码存储在32位字边界内，并且（ 2）单个32位指令代码完整地存储在32位字边界内。分支目的地址仅在32位字边界上指定。每个指令代码的MSB用作1位指令长度标识符，用于控制指令代码的执行顺序。这提供了从处理器内的指令获取部分到指令解码部分的两个传送路径，实现了代码侧的减少和硬件的数量以及相应的操作速度的提高。

3. 发明授权

US5872903A Integrated circuit device with a memory that preserves its content independently of a synchronizing signal when given a self-control request 失效
标题翻译：具有存储器的集成电路器件，当给定自我控制请求时，该存储器可独立于同步信号保持其内容
公开(公告)号：US5872903A
公开(公告)日：1999-02-16
申请号：US805350
申请日：1997-02-24
申请人： Shunichi Iwata , Mitsugu Satou
发明人： Shunichi Iwata , Mitsugu Satou
IPC分类号： G06F1/32 , G05B15/02 , G05B19/02 , G05B19/05 , G06F1/04 , G06F1/26 , G06F12/08 , G06F15/78 , G06F15/16
CPC分类号： G06F12/0891 , G06F1/26 , Y02B60/1225
摘要： When a CPU (1) writes "10" into a register (RG) provided in a controller (5), an AND gate (10) receives a CPU clock mask signal (CMS1) having the logic of "0" by one of its input terminals and accordingly cuts off the supply of a clock signal CLK to the CPU (1). Then, the CPU (1) is suspended, thereby reducing power consumption of the CPU (1). To return out of this state, a user has only to input an interrupt request to the controller (5) through a terminal (T1). Receiving the request, the controller (5) outputs the CPU clock mask signal (CMS1) having the logic of "1" to one of the input terminals of the AND gate (10) so as to supply the CPU (1) with the clock signal (CLK) again. Upon restarting the supply of the clock signal (CLK), the CPU (1) starts an operation to implement the interrupt request. With this configuration, an integrated circuit device including a control circuit for controlling operations of a processing circuit and a memory circuit with excellent operability can be provided.
摘要翻译：当CPU（1）将“10”写入到控制器（5）中提供的寄存器（RG）中时，与门（10）通过其中的一个接收具有逻辑“0”的CPU时钟屏蔽信号（CMS1）输入端子，从而切断向CPU（1）提供时钟信号CLK。然后，CPU（1）暂停，从而降低CPU（1）的功耗。为了退出该状态，用户仅通过终端（T1）向控制器（5）输入中断请求。接收到该请求后，控制器（5）将具有逻辑“1”的CPU时钟屏蔽信号（CMS1）输出到与门（10）的输入端之一，以向CPU（1）提供时钟信号（CLK）。在重新启动时钟信号（CLK）的提供时，CPU（1）开始执行中断请求的操作。利用这种配置，可以提供一种集成电路装置，其包括用于控制处理电路的操作的控制电路和具有优异的可操作性的存储电路。

4. 发明授权

US5121474A Bit string data processor using dynamically addressable bit locations in memory so overlapping strings do not destroy data in memory 失效
标题翻译：位串数据处理器在内存中使用动态可寻址的位位置，因此重叠的字符串不会破坏内存中的数据
公开(公告)号：US5121474A
公开(公告)日：1992-06-09
申请号：US677363
申请日：1991-03-26
申请人： Ken Sakamura , Toru Shimizu , Shunichi Iwata , Tatsuya Enomoto
发明人： Ken Sakamura , Toru Shimizu , Shunichi Iwata , Tatsuya Enomoto
IPC分类号： G06F7/00 , G06F7/76 , G06F9/305 , G06F9/308 , G06F9/34 , G06T1/20
CPC分类号： G06F9/30018
摘要： A data processor in accordance with the present invention can normally operate bit-string data while avoiding a breakage of the data even in the case where a read-out area of the bit string and a write-in area thereof are overlapped by each other by providing an operation code of an instruction with an option designating the direction of bit processing.
摘要翻译：根据本发明的数据处理器即使在位串的读出区域和写入区域彼此重叠的情况下也可以正常地操作位串数据，同时避免数据的破坏，提供具有指定位处理方向的选项的指令的操作代码。

5. 发明授权

US08423850B2 System debugging method, system debugging equipment, processor, wireless-communications interface IC and interface method thereof 有权
标题翻译：系统调试方法，系统调试设备，处理器，无线通信接口IC及其接口方法
公开(公告)号：US08423850B2
公开(公告)日：2013-04-16
申请号：US12514023
申请日：2007-11-08
申请人： Shunichi Iwata , Yoichi Takahata , Toshihiko Sugahara , Yutaka Takikawa , Yoshihiro Shimizu , Hiroki Ishikuro , Tadahiro Kuroda
发明人： Shunichi Iwata , Yoichi Takahata , Toshihiko Sugahara , Yutaka Takikawa , Yoshihiro Shimizu , Hiroki Ishikuro , Tadahiro Kuroda
IPC分类号： G01R31/28 , G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H03C1/62 , H04B17/00 , H04B10/08 , H04W24/00
CPC分类号： G06F11/3656 , G01R1/07 , G01R31/3025 , G01R31/31705 , H04W28/18 , H04W76/10
摘要： A pulse transmission technique is used for wireless communication between a microcomputer (13) having a debugging support circuit (17) and a debugger (13). The pulse transmission technique is based on magnetic field coupling between a first coil (14) provided for the microcomputer and a second coil (8) coupled with the debugger. During an initialization operation, the microcomputer performs a process of configuring a communication condition of the wireless communication to perform the wireless communication. The microcomputer awaits control from the debugger when the microcomputer establishes communication with the debugger. The debugger awaits establishment of the communication and proceeds to control of the microcomputer in accordance with the wireless communication. It is possible to provide contactless interface for system debugging without the need for a large antenna or a large-scale circuit for modulation and demodulation.
摘要翻译：脉冲传输技术用于具有调试支持电路（17）的微型计算机（13）和调试器（13）之间的无线通信。脉冲传输技术基于为微型计算机提供的第一线圈（14）和与调试器耦合的第二线圈（8）之间的磁场耦合。在初始化操作期间，微型计算机执行配置无线通信的通信条件以执行无线通信的处理。当微型计算机与调试器建立通信时，微机等待调试器的控制。调试器等待建立通信，并根据无线通信进行微型计算机的控制。可以提供用于系统调试的非接触式接口，而无需大型天线或用于调制和解调的大规模电路。

6. 发明授权

US07752527B2 Microcontroller and RAM 失效
标题翻译：微控制器和RAM
公开(公告)号：US07752527B2
公开(公告)日：2010-07-06
申请号：US11604806
申请日：2006-11-28
申请人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
发明人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
IPC分类号： G11C29/00
CPC分类号： G06F11/167 , G06F11/08 , G06F11/183
摘要： A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
摘要翻译：提供了一种微控制器，其中硬件的增加被抑制，并且可以提高对RAM的软件错误的数据校正能力。执行根据程序的处理的微控制器包括CPU和RAM，用于存储由CPU处理的数据，其中在RAM中定义复用区域，并且当这些区域被访问时，访问由CPU输出的地址和执行通过向CPU输出的地址添加或减去某个值而获得的地址的复制访问。通过这种方式，可以将相同的数据存储在多个区域中，并且可以提高可靠性。

7. 发明申请

US20100040123A1 SYSTEM DEBUGGING METHOD, SYSTEM DEBUGGING EQUIPMENT, PROCESSOR, WIRELESS-COMMUNICATIONS INTERFACE IC AND INTERFACE METHOD THEREOF 有权
标题翻译：系统调试方法，系统调试设备，处理器，无线通信接口IC及其接口方法
公开(公告)号：US20100040123A1
公开(公告)日：2010-02-18
申请号：US12514023
申请日：2007-11-08
申请人： Shunichi Iwata , Yoichi Takahata , Toshihiko Sugahara , Yutaka Takikawa , Yoshihiro Shimizu , Hiroki Ishikuro , Tadahiro Kuroda
发明人： Shunichi Iwata , Yoichi Takahata , Toshihiko Sugahara , Yutaka Takikawa , Yoshihiro Shimizu , Hiroki Ishikuro , Tadahiro Kuroda
IPC分类号： H04B1/38 , G06F11/07 , H04L27/00
CPC分类号： G06F11/3656 , G01R1/07 , G01R31/3025 , G01R31/31705 , H04W28/18 , H04W76/10
摘要： A pulse transmission technique is used for wireless communication between a microcomputer (13) having a debugging support circuit (17) and a debugger (13). The pulse transmission technique is based on magnetic field coupling between a first coil (14) provided for the microcomputer and a second coil (8) coupled with the debugger. During an initialization operation, the microcomputer performs a process of configuring a communication condition of the wireless communication to perform the wireless communication. The microcomputer awaits control from the debugger when the microcomputer establishes communication with the debugger. The debugger awaits establishment of the communication and proceeds to control of the microcomputer in accordance with the wireless communication. It is possible to provide contactless interface for system debugging without the need for a large antenna or a large-scale circuit for modulation and demodulation.
摘要翻译：脉冲传输技术用于具有调试支持电路（17）的微型计算机（13）和调试器（13）之间的无线通信。脉冲传输技术基于为微型计算机提供的第一线圈（14）和与调试器耦合的第二线圈（8）之间的磁场耦合。在初始化操作期间，微型计算机执行配置无线通信的通信条件以执行无线通信的处理。当微型计算机与调试器建立通信时，微机等待调试器的控制。调试器等待建立通信，并根据无线通信进行微型计算机的控制。可以提供用于系统调试的非接触式接口，而无需大型天线或用于调制和解调的大规模电路。

8. 发明申请

US20080222336A1 DATA PROCESSING SYSTEM 审中-公开
标题翻译：数据处理系统
公开(公告)号：US20080222336A1
公开(公告)日：2008-09-11
申请号：US12014069
申请日：2008-01-14
申请人： Yoshikazu KIYOSHIGE , Shunichi Iwata , Kesami Hagiwara , Akihiko Tomita
发明人： Yoshikazu KIYOSHIGE , Shunichi Iwata , Kesami Hagiwara , Akihiko Tomita
IPC分类号： G06F9/30 , G06F13/14 , G06F9/302
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3851 , G06F9/3877 , G06F9/3885 , G06F9/3891
摘要： To allow to use arithmetic circuits of sharable resources by priority with a simple procedure. In a data processing system including central processing units and a plurality of arithmetic circuits, wherein the central processing units are able to supply a command to one arithmetic circuit based on one fetched instruction and supply a command to other arithmetic circuit based on other fetched instruction, a memory circuit is provided which is used to store first information indicating which arithmetic circuit is executing a command, and second information indicating which central processing unit has reserved the arithmetic circuit for execution of the next command. When the arithmetic circuit is already executing a command, reservation of the arithmetic circuit for execution of the next command using the second information of the memory circuit, makes it possible, after the execution, to assign operation commands fast to the arithmetic circuits and cause them to execute the commands.
摘要翻译：允许以简单的过程优先使用可共享资源的算术电路。在包括中央处理单元和多个算术电路的数据处理系统中，其中中央处理单元能够基于一个获取的指令向一个算术电路提供命令，并且基于其他获取的指令向其他算术电路提供命令，提供了一种存储电路，用于存储指示哪个运算电路正在执行命令的第一信息，以及指示哪个中央处理单元预留了用于执行下一个命令的运算电路的第二信息。当算术电路已经在执行命令时，使用存储电路的第二信息来预约用于执行下一个命令的运算电路，使执行后能够将运算命令快速地分配给运算电路并使它们执行命令。

9. 发明授权

US06961872B2 Microcomputer and debugging system 失效
标题翻译：微电脑调试系统
公开(公告)号：US06961872B2
公开(公告)日：2005-11-01
申请号：US10193325
申请日：2002-07-12
申请人： Osamu Yamamoto , Shunichi Iwata
发明人： Osamu Yamamoto , Shunichi Iwata
IPC分类号： G06F11/28 , G06F11/34 , G06F11/36 , G06F11/00
CPC分类号： G06F11/3636 , G06F11/28 , G06F11/3648
摘要： A microcomputer according to the present invention includes: collecting unit for generating and collecting a series of trace information for each execution process of a program to be evaluated in a preset sampling period for a predetermined number of repetitions; outputting circuit for outputting the series of the trace information for each repetition; and decimating circuit for deleting any of the trace information collected at each repetition so that the outputting circuit can output all of the trace information to be collected within the sampling period when the collecting circuit has finished repetitive collection process.
摘要翻译：根据本发明的微型计算机包括：收集单元，用于为预定次数的重复的预设采样周期中的待评估程序的每个执行处理生成和收集一系列跟踪信息; 输出电路，用于输出每个重复的一系列跟踪信息; 以及抽取电路，用于删除在每次重复时收集的任何跟踪信息，使得当收集电路完成重复收集处理时，输出电路可以在采样周期内输出要采集的所有跟踪信息。

10. 发明授权

US5669012A Data processor and control circuit for inserting/extracting data to/from an optional byte position of a register 失效
标题翻译：数据处理器和控制电路，用于从寄存器的可选字节位置插入/提取数据
公开(公告)号：US5669012A
公开(公告)日：1997-09-16
申请号：US720455
申请日：1996-09-30
申请人： Toru Shimizu , Shunichi Iwata , Toshio Doi , Shigeo Mizugaki
发明人： Toru Shimizu , Shunichi Iwata , Toshio Doi , Shigeo Mizugaki
IPC分类号： G06F7/00 , G06F9/30 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/34 , G06F9/35
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30167
摘要： A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of a general register file or a memory) is inserted in an optional bit area (determined by the value of the first operation code part) of a destination register according to the decoding result, and an optional bit area (determined by the value of the second operation code part) of a source register is extracted and stored in an optional bit area of destination (a register of the general register file or the memory), thereby making it possible to "process the insertion and extraction operations to and from optional byte positions of registers" at a high speed with short instruction code size.
摘要翻译：一种数据处理器，其具有对包括两个操作码部分的指令代码，源操作数指定部分和目的地操作数指定部分进行解码的微解码器，其中源数据的可选位区（通用寄存器文件或存储器的寄存器）根据解码结果插入到目的地寄存器的可选位区域（由第一操作码部分的值确定）和源寄存器的可选位区域（由第二操作码部分的值确定）被提取并存储在目的地的可选位区（通用寄存器文件或存储器的寄存器）中，从而使得可以以高速“处理到寄存器的可选字节位置的插入和提取操作”成为可能，短指令代码大小。

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