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41. 发明授权

US06194764B1 Integrated semiconductor circuit with protection structure for protecting against electrostatic discharge 有权
标题翻译：具有防止静电放电的保护结构的集成半导体电路
公开(公告)号：US06194764B1
公开(公告)日：2001-02-27
申请号：US09163881
申请日：1998-09-30
申请人： Harald Gossner , Matthias Stecher , Werner Schwetlick
发明人： Harald Gossner , Matthias Stecher , Werner Schwetlick
IPC分类号： H01L2362
CPC分类号： H01L27/0248 , H01L27/0755 , H01L2924/0002 , H01L2924/00
摘要： An integrated semiconductor circuit has a protection structure for protecting against electrostatic discharge. The protection element has at least one integrated vertical protection transistor, whose load path is connected between the terminal pad and a potential rail. The base of the vertical npn bipolar transistor is controlled by a diode at breakdown, whose breakdown voltage is above the holding voltage of the npn bipolar transistors. By suitably choosing the location of the base contact, of the pn junction of the breakdown diode, and of the emitter, a desired adjustment of the trigger current is possible. Thus a variation in the voltage drop at the base is achieved which enables a current flow. The signal voltage requirements can be met and at the same time, an optimization of the ESD strength is achieved. The control or trigger sensitivity of the base can also be adjusted by means of an integrated resistor, which is disposed in the base zone.
摘要翻译：集成半导体电路具有防止静电放电的保护结构。保护元件具有至少一个集成的垂直保护晶体管，其负载路径连接在端子焊盘和电位导轨之间。垂直npn双极晶体管的基极由击穿时的二极管控制，其击穿电压高于npn双极晶体管的保持电压。通过适当选择基极触点，击穿二极管的pn结和发射极的位置，触发电流的期望调节是可能的。因此，实现了基极处的电压降的变化，其使电流流动。可以满足信号电压要求，同时实现ESD强度的优化。基座的控制或触发灵敏度也可以通过设置在基区中的集成电阻来调节。

42. 发明申请

US20150214188A1 FLEXIBLY-WRAPPED INTEGRATED CIRCUIT DIE 有权
标题翻译：柔性包裹式集成电路
公开(公告)号：US20150214188A1
公开(公告)日：2015-07-30
申请号：US14368434
申请日：2013-12-19
申请人： Sven Albers , Michael Skinner , Hnas-Joachim Barth , Peter Baumgartner , Harald Gossner
发明人： Sven Albers , Michael Skinner , Hnas-Joachim Barth , Peter Baumgartner , Harald Gossner
IPC分类号： H01L25/065 , H01L27/02 , H01L23/00
CPC分类号： H01L25/0652 , H01L23/367 , H01L23/3675 , H01L23/5226 , H01L23/5227 , H01L23/552 , H01L23/562 , H01L23/564 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L25/065 , H01L25/0657 , H01L27/0207 , H01L29/0657 , H01L2223/6677 , H01L2224/131 , H01L2224/1319 , H01L2224/16105 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/48091 , H01L2224/481 , H01L2224/48106 , H01L2224/4813 , H01L2224/48137 , H01L2224/48145 , H01L2224/48225 , H01L2224/48227 , H01L2224/48482 , H01L2224/49 , H01L2224/73257 , H01L2224/81001 , H01L2224/81007 , H01L2224/8114 , H01L2224/81801 , H01L2224/8185 , H01L2224/85801 , H01L2225/06506 , H01L2225/0651 , H01L2225/06551 , H01L2225/06589 , H01L2924/00014 , H01L2924/19104 , H01L2224/45099 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2924/014 , H01L2924/00012
摘要： Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.
摘要翻译：公开了一种柔性包裹的集成电路管芯器件的实施例和用于将柔性封装的集成电路管芯安装到衬底的方法。在一些实施例中，柔性包裹的集成电路管芯器件包括基板和柔性集成电路管芯，所述基板和基板相对于基板的表面以基本垂直的取向联接到基板。

43. 发明授权

US08963201B2 Tunable fin-SCR for robust ESD protection 有权
标题翻译：可调谐鳍片SCR，用于强大的ESD保护
公开(公告)号：US08963201B2
公开(公告)日：2015-02-24
申请号：US13411667
申请日：2012-03-05
申请人： Mayank Shrivastava , Christian Russ , Harald Gossner
发明人： Mayank Shrivastava , Christian Russ , Harald Gossner
IPC分类号： H01L29/66
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/0619 , H01L29/0634 , H01L29/0657 , H01L29/0692 , H01L29/1016 , H01L29/102 , H01L29/744
摘要： One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种硅控整流器（SCR）。 SCR包括在阳极和阴极之间延伸并且包括其间的结区域的纵向硅翅片。一个或多个第一横向翼片在位于阳极和接合区域之间的一个或多个相应的攻丝点处横穿纵向翅片。还公开了其它装置和方法。

44. 发明授权

US08785968B2 Silicon controlled rectifier (SCR) device for bulk FinFET technology 有权
标题翻译：用于散装FinFET技术的可控硅整流器（SCR）器件
公开(公告)号：US08785968B2
公开(公告)日：2014-07-22
申请号：US13646799
申请日：2012-10-08
申请人： Mayank Shrivastava , Harald Gossner
发明人： Mayank Shrivastava , Harald Gossner
IPC分类号： H01L29/66
CPC分类号： H01L27/0817 , H01L21/845 , H01L27/1211
摘要： Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.
摘要翻译：一些方面涉及设置在半导体衬底上的半导体器件。该器件包括横向围绕半导体鳍片的基底部分的STI区域。具有第一导电类型的阳极区域和具有第二导电类型的阴极区域布置在半导体鳍片的上部。具有第二导电类型的第一掺杂基极区布置在阳极区域下方的翅片的底部。具有第一导电类型的第二掺杂基区布置在阴极区下方的鳍的底部。电流控制单元设置在阳极区域和阴极区域之间。电流控制单元被布置为基于触发信号来选择性地启用和禁止鳍的上部中的电流。还公开了其它装置和方法。

45. 发明授权

US08455949B2 ESD protection element and ESD protection device for use in an electrical circuit 有权
标题翻译： ESD保护元件和用于电路的ESD保护器件
公开(公告)号：US08455949B2
公开(公告)日：2013-06-04
申请号：US11803169
申请日：2007-05-11
申请人： Harald Gossner , Christian Russ
发明人： Harald Gossner , Christian Russ
IPC分类号： H01L29/78
CPC分类号： H01L23/60 , H01L27/0262 , H01L29/0657 , H01L29/0692 , H01L29/7436 , H01L29/749 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection element for use in an electrical circuit having a fin structure or a fully depleted silicon-on-insulator structure. The fin structure or the fully depleted silicon-on-insulator structure contains a first connection region having a first conductivity type; a second connection region having a second conductivity type, which is opposite to the first conductivity type; and also a plurality of body regions which are formed alongside one another and which are formed between the first connection region and the second connection region. The body regions alternately have the first conductivity type and the second conductivity type. The ESD protection element has at least one gate region formed on or above at least one of the plurality of body regions, and also at least one gate control device which is electrically coupled to the at least one gate region.
摘要翻译：一种用于具有翅片结构或完全耗尽的绝缘体上硅结构的电路中的ESD保护元件。翅片结构或完全耗尽的绝缘体上的结构包含具有第一导电类型的第一连接区域; 具有与第一导电类型相反的第二导电类型的第二连接区域; 以及形成在第一连接区域和第二连接区域之间的多个体区域。身体区域交替地具有第一导电类型和第二导电类型。 ESD保护元件具有形成在多个主体区域中的至少一个上方或上方的至少一个栅极区域，以及至少一个电连接至该至少一个栅极区域的栅极控制装置。

46. 发明授权

US08455947B2 Device and method for coupling first and second device portions 有权
标题翻译：用于联接第一和第二装置部分的装置和方法
公开(公告)号：US08455947B2
公开(公告)日：2013-06-04
申请号：US12388479
申请日：2009-02-18
申请人： Mayank Shrivastava , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao , Maryam Shojaei Baghini
发明人： Mayank Shrivastava , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao , Maryam Shojaei Baghini
IPC分类号： H01L29/00
CPC分类号： H01L27/0262 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： This disclosure relates to devices and methods relating to coupled first and second device portions.
摘要翻译：本公开涉及与耦合的第一和第二设备部分有关的设备和方法。

47. 发明授权

US08450156B2 Method for producing a thyristor 有权
标题翻译：晶闸管的制造方法
公开(公告)号：US08450156B2
公开(公告)日：2013-05-28
申请号：US13481969
申请日：2012-05-29
申请人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
发明人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
IPC分类号： H01L21/332
CPC分类号： H01L29/78624 , H01L21/26586 , H01L21/84 , H01L27/0262 , H01L27/1203 , H01L29/66393 , H01L29/7436 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.
摘要翻译：在晶闸管的制造方法中，在基板上或上方形成有第一和第二连接区域，第一连接区域掺杂有第一导电类型的掺杂剂原子，并且第二连接区域掺杂有第二导电类型的掺杂剂原子; 第一和第二体区域形成在连接区域之间，其中第一体区形成在第一连接区域和第二体区域之间，第二体区域形成在第一体区域和第二连接区域之间; 所述第一体区掺杂有所述第二导电类型的掺杂剂原子，并且所述第二体区掺杂有所述第一导电类型的掺杂剂原子，其中所述掺杂剂原子在每种情况下使用Vt注入方法引入相应的体区; 在身体区域上或上方形成栅极区域。

48. 发明授权

US08405121B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US08405121B2
公开(公告)日：2013-03-26
申请号：US12369821
申请日：2009-02-12
申请人： Harald Gossner , Ramgopal Rao , Angada Sachid , Ashish Pal , Ram Asra
发明人： Harald Gossner , Ramgopal Rao , Angada Sachid , Ashish Pal , Ram Asra
IPC分类号： H01L29/66
CPC分类号： H01L29/165 , H01L21/26586 , H01L29/0657 , H01L29/083 , H01L29/0834 , H01L29/66356 , H01L29/7391
摘要： In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.
摘要翻译：在一个实施例中，提供了半导体器件。半导体器件可以包括具有主处理表面的衬底，包括第一导电类型的第一材料的第一源极/漏极区域，包括第二导电类型的第二材料的第二源极/漏极区域，其中第二导电类型不同于第一导电类型，电耦合在第一源极/漏极区域和第二源极/漏极区域之间的主体区域，其中主体区域在第一方向上比第一源极/漏极区域在第一方向垂直于基板的主处理表面，设置在主体区域上的栅极电介质和设置在栅极电介质上的栅极区域，其中栅极区域与第一源极/漏极区域的至少一部分重叠，的身体区域在第一个方向。

49. 发明申请

US20120252172A1 Method for producing a thyristor 有权
标题翻译：晶闸管的制造方法
公开(公告)号：US20120252172A1
公开(公告)日：2012-10-04
申请号：US13481969
申请日：2012-05-29
申请人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
发明人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
IPC分类号： H01L21/332
CPC分类号： H01L29/78624 , H01L21/26586 , H01L21/84 , H01L27/0262 , H01L27/1203 , H01L29/66393 , H01L29/7436 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.
摘要翻译：在晶闸管的制造方法中，在基板上或上方形成有第一和第二连接区域，第一连接区域掺杂有第一导电类型的掺杂剂原子，并且第二连接区域掺杂有第二导电类型的掺杂剂原子; 第一和第二体区域形成在连接区域之间，其中第一体区形成在第一连接区域和第二体区域之间，第二体区域形成在第一体区域和第二连接区域之间; 所述第一体区掺杂有所述第二导电类型的掺杂剂原子，并且所述第二体区掺杂有所述第一导电类型的掺杂剂原子，其中所述掺杂剂原子在每种情况下都使用Vt注入法引入所述体区; 在身体区域上或上方形成栅极区域。

50. 发明申请

US20120199878A1 Drain Extended Field Effect Transistors and Methods of Formation Thereof 有权
标题翻译：排水扩展场效应晶体管及其形成方法
公开(公告)号：US20120199878A1
公开(公告)日：2012-08-09
申请号：US13020368
申请日：2011-02-03
申请人： Mayank Shrivastava , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao
发明人： Mayank Shrivastava , Cornelius Christian Russ , Harald Gossner , Ramgopal Rao
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1095 , H01L21/26513 , H01L27/088 , H01L29/0634 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/0873 , H01L29/0878 , H01L29/1054 , H01L29/165 , H01L29/267 , H01L29/41775 , H01L29/45 , H01L29/456 , H01L29/665 , H01L29/66575 , H01L29/66659 , H01L29/78 , H01L29/7816 , H01L29/7835 , H01L29/7842
摘要： In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.
摘要翻译：在本发明的实施例中，半导体器件包括具有第一掺杂类型的第一区域，具有设置在第一区域中的第一掺杂类型的沟道区域和具有第二掺杂类型的逆行阱。第二掺杂类型与第一掺杂类型相反。逆行井具有具有第一峰掺杂的较浅层和比第一峰掺杂高的第二峰掺杂的较深层。该装置还包括在逆行井上具有第二掺杂型的漏极区。延伸的漏极区域设置在逆行阱中，并且将沟道区域与漏极区域耦合。隔离区域设置在延伸漏极区域的栅极重叠区域和漏极区域之间。漏区的长度大于隔离区的深度。

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