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41. 发明授权

US06979878B1 Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites 失效
标题翻译：隔离结构在隔离槽的顶角处注入硅原子填充空位和间隙位置
公开(公告)号：US06979878B1
公开(公告)日：2005-12-27
申请号：US09217213
申请日：1998-12-21
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。

42. 发明授权

US06451657B1 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant 失效
标题翻译：具有由横向扩散的氮植入物限定的超短沟道长度的晶体管
公开(公告)号：US06451657B1
公开(公告)日：2002-09-17
申请号：US09781044
申请日：2001-02-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28132 , Y10S257/90
摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.
摘要翻译：公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。在轻掺杂的半导体衬底上形成栅氧化层。然后在栅极氧化物层上沉积栅极导体层。栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。热退火降低了无氮区域的宽度。然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。

43. 发明授权

US06258646B1 CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof 有权
标题翻译： CMOS集成电路和用于在注入PMOS晶体管区域之前注入NMOS晶体管区域以优化其热扩散率的方法
公开(公告)号：US06258646B1
公开(公告)日：2001-07-10
申请号：US09149631
申请日：1998-09-08
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823814 , Y10S257/90
摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.
摘要翻译：提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

44. 发明授权

US06245652B1 Method of forming ultra thin gate dielectric for high performance semiconductor devices 有权
标题翻译：形成用于高性能半导体器件的超薄栅极电介质的方法
公开(公告)号：US06245652B1
公开(公告)日：2001-06-12
申请号：US09598531
申请日：2000-06-21
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
IPC分类号： H01L213205
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention is directed to a semiconductor device having an ultra thin, reliable gate dielectric and a method for making same. In one illustrative embodiment, the present method comprises forming a first layer of nitrogen doped silicon dioxide above a semiconducting substrate, reducing the thickness of the first layer, forming a second layer comprised of a material having a dielectric constant greater than seven above the first layer of silicon dioxide. The method further comprises forming a third layer comprised of a gate conductor material above the second layer, and patterning the first, second and third layers to define a gate conductor and a composite gate dielectric comprised of the first and second layers, and forming at least one source/drain region. The semiconductor device has a composite gate dielectric comprised of a first process layer comprised of a nitrogen doped oxide and a second process layer comprised of a material having a dielectric constant greater than seven. The device further comprises a gate conductor positioned above the composite gate dielectric, and at least one source/drain region formed in the substrate.
摘要翻译：本发明涉及具有超薄，可靠的栅极电介质的半导体器件及其制造方法。在一个说明性实施例中，本方法包括在半导体衬底上形成氮掺杂二氧化硅的第一层，减小第一层的厚度，形成第二层，第二层由介电常数大于第一层以上的材料构成的二氧化硅。该方法还包括在第二层上形成由栅极导体材料构成的第三层，以及对第一层，第二层和第三层进行构图以限定由第一层和第二层构成的栅极导体和复合栅极电介质，并形成至少一个源/漏区。该半导体器件具有复合栅极电介质，该复合栅极电介质由包含氮掺杂氧化物的第一工艺层和由介电常数大于7的材料构成的第二工艺层组成。该器件还包括位于复合栅极电介质上方的栅极导体，以及形成在衬底中的至少一个源极/漏极区。

45. 发明授权

US06200865B1 Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate 有权
标题翻译：使用牺牲介电结构形成具有自对准阈值的半导体器件调整并覆盖低电阻栅极
公开(公告)号：US06200865B1
公开(公告)日：2001-03-13
申请号：US09205443
申请日：1998-12-04
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21336
CPC分类号： H01L29/66537 , H01L21/28273 , H01L29/42324 , H01L29/66545 , H01L29/6659 , H01L29/66825
摘要： A semiconductor device is provided and formed using self-aligned low-resistance gates within a metal-oxide semiconductor (MOS) process. A sacrificial dielectric gate structure is formed on a semiconductor substrate instead of a conventional gate dielectric/gate conductor stack. After forming junction regions within a semiconductor substrate, the gate structure is removed to form a trench within a dielectric formed above the substrate. A low-resistance gate material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The gate material can take various forms, including a single layer or multiple metal and/or dielectric layers interposed throughout the as-filled trench. The gate formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻栅极提供并形成半导体器件。在半导体衬底上形成牺牲电介质栅极结构，而不是传统的栅极介质/栅极导体堆叠。在半导体衬底中形成结区之后，去除栅极结构，以在衬底之上形成的电介质内形成沟槽。然后可以在沟槽内，即在去除栅极导体的区域中布置低电阻栅极材料。栅极材料可以采取各种形式，包括插入整个填充沟槽中的单层或多个金属和/或介电层。栅极形成发生在高温循环之后，通常与激活以前注入的结或生长的栅极电介质相关联。因此，可以使用诸如铜或铜合金的低温金属。

46. 发明授权

US06188114B1 Method of forming an insulated-gate field-effect transistor with metal spacers 有权
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US06188114B1
公开(公告)日：2001-02-13
申请号：US09204016
申请日：1998-12-01
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31119
CPC分类号： H01L29/41783 , H01L29/41775 , H01L29/66575 , H01L29/6659
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

47. 发明授权

US06177687B1 Semiconductor device having gate electrode shared between two sets of active regions and fabrication thereof 有权
标题翻译：具有在两组有源区域之间共享的栅电极的半导体器件及其制造
公开(公告)号：US06177687B1
公开(公告)日：2001-01-23
申请号：US09201995
申请日：1998-12-01
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L2916
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Semiconductor devices having a gate electrode shared by two sets of active regions and methods of manufacture thereof are provided. In one embodiment, a first substrate is provided and a gate electrode is disposed over the first substrate. A second substrate is disposed over the gate electrode. A first set of active regions is disposed in portions of the first substrate adjacent the gate electrode and a second set of active regions is disposed above the gate electrode and adjacent the second substrate. The two sets of active regions may be coupled together or used separately.
摘要翻译：提供具有由两组活性区域共享的栅电极的半导体器件及其制造方法。在一个实施例中，提供第一基板并且在第一基板上设置栅电极。第二衬底设置在栅电极之上。第一组有源区设置在与栅电极相邻的第一衬底的部分中，并且第二组有源区设置在栅电极上方并与第二衬底相邻。两组有源区可以耦合在一起或单独使用。

48. 发明授权

US6166354A System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication 失效
标题翻译：用于半导体制造中退火的原位监测和控制的系统和装置
公开(公告)号：US6166354A
公开(公告)日：2000-12-26
申请号：US876381
申请日：1997-06-16
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： C30B31/12 , C30B31/18 , F27B5/14
CPC分类号： C30B31/18 , C30B31/12
摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.
摘要翻译：在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。监测表面光电压测量，检测退火时间，并控制所选择的过退火。执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。检测点也用于终止退火过程以最小化Dt。

49. 发明授权

US6162688A Method of fabricating a transistor with a dielectric underlayer and device incorporating same 有权
标题翻译：制造具有电介质底层的晶体管的方法和结合其的器件
公开(公告)号：US6162688A
公开(公告)日：2000-12-19
申请号：US231427
申请日：1999-01-14
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/266 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/06 , H01L29/49 , H01L29/51 , H01L29/786 , H01L21/00
CPC分类号： H01L21/28194 , H01L21/266 , H01L21/268 , H01L21/28158 , H01L21/28202 , H01L21/823842 , H01L27/0688 , H01L29/4908 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545 , H01L29/66757 , H01L29/78636
摘要： A method is provided for fabricating a transistor, the method including forming a dielectric layer above a structure, forming a first polysilicon layer above the dielectric layer and forming a sacrificial region above the first polysilicon layer. The method also includes forming a second polysilicon layer above the first polysilicon layer and adjacent the sacrificial region. The method further includes removing the sacrificial region to form an opening in the second polysilicon layer, the opening having sidewalls, and forming dielectric spacers on the sidewalls of the opening. In addition, the method includes forming a gate dielectric within the opening above the first polysilicon layer and forming a gate conductor above the gate dielectric.
摘要翻译：提供了一种用于制造晶体管的方法，所述方法包括在结构之上形成电介质层，在电介质层上方形成第一多晶硅层，并在第一多晶硅层上方形成牺牲区域。该方法还包括在第一多晶硅层上形成第二多晶硅层并且邻近牺牲区。该方法还包括去除牺牲区域以在第二多晶硅层中形成开口，该开口具有侧壁，并在开口的侧壁上形成电介质间隔物。此外，该方法包括在第一多晶硅层上方的开口内形成栅极电介质，并在栅极电介质上方形成栅极导体。

50. 发明授权

US6150708A Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density 有权
标题翻译：先进的CMOS电路，利用晶片表面的两侧增加电路密度
公开(公告)号：US6150708A
公开(公告)日：2000-11-21
申请号：US191305
申请日：1998-11-13
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L25/00
CPC分类号： H01L21/8221 , H01L27/0694 , H01L27/092
摘要： An integrated circuit employing both sides of a base substrate or wafer and a method of making the same are provided. In one aspect, the integrated circuit includes a base substrate that has a first side and a second side opposite the first side. The first side has a first semiconductor layer and a first isolation structure positioned thereon wherein the first side surrounds the first semiconductor layer. The second side has a second semiconductor layer and a second isolation structure positioned thereon wherein the second isolation structure surrounds the second semiconductor layer. A first circuit device is positioned on the first semiconductor layer. A second circuit device is positioned on the second semiconductor layer. The method enables simultaneous processing of both sides of a given wafer. Fabrication efficiency is increased through higher throughput and much higher yields per wafer.
摘要翻译：提供采用基底或晶片两侧的集成电路及其制造方法。一方面，集成电路包括具有第一侧和与第一侧相对的第二侧的基底基板。第一侧具有第一半导体层和位于其上的第一隔离结构，其中第一侧围绕第一半导体层。第二侧具有第二半导体层和位于其上的第二隔离结构，其中第二隔离结构围绕第二半导体层。第一电路器件位于第一半导体层上。第二电路器件位于第二半导体层上。该方法能够同时处理给定晶片的两侧。通过更高的产量和更高的每片晶圆产量提高制造效率。

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