专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06977203B2 Method of forming narrow trenches in semiconductor substrates 有权
标题翻译：在半导体衬底中形成窄沟槽的方法
公开(公告)号：US06977203B2
公开(公告)日：2005-12-20
申请号：US10010162
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/308 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/311 , H01L21/3205
CPC分类号： H01L21/3088 , H01L21/3086
摘要： A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
摘要翻译：一种在半导体衬底内形成沟槽的方法。该方法例如包括以下：（a）提供半导体衬底; （b）提供在半导体衬底上具有第一孔的图案化的第一CVD沉积掩模材料层; （c）在所述第一掩蔽材料层上沉积第二CVD沉积的掩模材料层; （d）蚀刻所述第二掩模材料层，直到在所述第一孔径内的所述第二掩模材料中产生比所述第一孔径窄的第二孔径; 以及（e）通过所述第二孔蚀刻所述半导体衬底，使得在所述半导体衬底中形成沟槽。在优选实施例中，本发明的方法用于形成沟槽MOSFET器件。

42. 发明授权

US06630402B2 Integrated circuit resistant to the formation of cracks in a passivation layer 失效
标题翻译：集成电路可抵抗钝化层中裂纹的形成
公开(公告)号：US06630402B2
公开(公告)日：2003-10-07
申请号：US09990460
申请日：2001-11-21
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L2100
CPC分类号： H01L21/76838 , H01L23/3171 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.
摘要翻译：在通过蚀刻和镶嵌技术制造的集成电路中，通常在集成到器件中的互连金属层周围的电介质材料中发生破裂，这可能是由于互连金属层到周围电介质材料的应力传递的结果。本发明通过提供一种互连金属层来解决这个问题，该互连金属层包括被认为能够减少传递到周围电介质层的应力的圆角。

43. 发明授权

US6046078A Semiconductor device fabrication with reduced masking steps 失效
标题翻译：具有减少掩蔽步骤的半导体器件制造
公开(公告)号：US6046078A
公开(公告)日：2000-04-04
申请号：US840350
申请日：1997-04-28
申请人： Koon Chong So , Fwu-Iuan Hshieh
发明人： Koon Chong So , Fwu-Iuan Hshieh
IPC分类号： H01L21/336
CPC分类号： H01L29/66719 , H01L29/66712
摘要： A method of forming a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device on a semiconductor substrate with reduced masking steps is disclosed. In the first method, the reduced masking steps are arranged in an optimal sequence in which the gate layer is patterned first as a self-aligned mask. The gate layer includes a plurality of gate segments separated by spacings. An active mask for defining active body regions is then patterned in the spacings of the gate layer to form a combination mask. Using the combination mask as a shield, body and source regions are ion-implanted into the substrate. During the formation of the active mask, remnant material of the active mask adheres to the boundaries of the gate segments to form a spacer layer which is utilized to alleviate the cell-to-cell encroachment problem due to the side diffusion effect of the body and source regions. In the second method, trenched gates are formed first on the semiconductor substrate prior to the patterning of the active mask which is used to perform multiple duties of defining the source and body diffusions, and the delineation of the active circuit region from the termination circuit region of the MOSFET device.
摘要翻译：公开了一种在具有减小的掩蔽步骤的半导体衬底上形成功率MOSFET（金属氧化物半导体场效应晶体管）器件的方法。在第一种方法中，减小的掩蔽步骤以最佳序列排列，其中栅极层首先被图案化为自对准掩模。栅极层包括由间隔隔开的多个栅极段。然后，用于限定活性体区域的活性掩模在栅极层的间隔中被图案化以形成组合掩模。使用组合掩模作为屏蔽，将体区和源区离子注入到衬底中。在活性掩模的形成期间，活性掩模的残留材料粘附到栅极段的边界以形成间隔层，其用于减轻由于身体的侧向扩散作用引起的细胞间侵扰问题，源地区。在第二种方法中，首先在半导体衬底上形成沟槽栅极，然后在用于执行定义源极和体扩散的多重任务的有源掩模的图案化之前，以及从终端电路区域描绘有源电路区域的MOSFET器件。

44. 发明授权

US07049194B2 Trench DMOS device with improved drain contact 有权
公开(公告)号：US07049194B2
公开(公告)日：2006-05-23
申请号：US10725326
申请日：2003-12-01
申请人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/41741 , H01L29/41766 , H01L29/7809 , H01L29/7811
摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

45. 发明授权

US06849899B2 High speed trench DMOS 有权
标题翻译：高速沟DMOS
公开(公告)号：US06849899B2
公开(公告)日：2005-02-01
申请号：US10673887
申请日：2003-09-29
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21/336 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4916 , H01L29/4925 , H01L29/4933
摘要： A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
摘要翻译：提供了制造沟槽DMOS的方法，其利用多硅化物和难熔技术来制造出具有低栅极电阻，低栅极电容，降低的分布式RC栅极传播延迟以及用于高频应用的改进的开关速度的沟槽DMOS。

46. 发明授权

US06621107B2 Trench DMOS transistor with embedded trench schottky rectifier 失效
标题翻译：沟槽DMOS晶体管采用嵌入式沟道肖特基整流器
公开(公告)号：US06621107B2
公开(公告)日：2003-09-16
申请号：US09938253
申请日：2001-08-23
申请人： Richard A. Blanchard , Fwu-Iuan Hshieh , Koon Chong So
发明人： Richard A. Blanchard , Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L2974
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/7806 , H01L29/872
摘要： A merged device is that comprises a plurality of MOSFET cells and a plurality of Schottky rectifier cells, as well as a method of designing and making the same. According to an embodiment of the invention, the MOSFET cells comprise: (a) a source region of first conductivity type formed within an upper portion of a semiconductor region, (b) a body region of second conductivity type formed within a middle portion of the semiconductor region, (c) a drain region of first conductivity type formed within a lower portion of the semiconductor region, and (d) a gate region provided adjacent the source region, the body region, and the drain region. The Schottky diode cells in this embodiment are disposed within a trench network and comprise a conductor portion in Schottky rectifying contact with the lower portion of the semiconductor region. At least one MOSFET cell gate region is positioned along a sidewall of the trench network and adjacent at least one Schottky diode cell in this embodiment.
摘要翻译：合并器件包括多个MOSFET单元和多个肖特基整流器单元，以及其设计和制造方法。根据本发明的实施例，MOSFET单元包括：（a）形成在半导体区域的上部内的第一导电类型的源极区域，（b）形成在半导体区域的中间部分内的第二导电类型的体区域半导体区域，（c）形成在半导体区域的下部内的第一导电类型的漏极区域，以及（d）设置在源极区域，体区域和漏极区域附近的栅极区域。该实施例中的肖特基二极管电池设置在沟槽网络内，并且包括与半导体区域的下部肖特基整流接触的导体部分。在该实施例中，至少一个MOSFET单元栅极区沿着沟槽网络的侧壁定位并且邻近至少一个肖特基二极管单元。

47. 发明授权

US06558984B2 Trench schottky barrier rectifier and method of making the same 有权
标题翻译：沟槽肖特基势垒整流器及其制作方法
公开(公告)号：US06558984B2
公开(公告)日：2003-05-06
申请号：US10078994
申请日：2002-02-19
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L21332
CPC分类号： H01L29/66143 , H01L29/417 , H01L29/872
摘要： A trench Schottky barrier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of a first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on the bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.
摘要翻译：沟槽肖特基势垒及其制造方法，其中整流器具有具有第一和第二相对面的半导体区域; 所述半导体区域具有与所述第一面相邻的第一导电类型的漂移区域和与所述第二面部相邻的所述第一导电类型的阴极区域; 漂移区具有比阴极区更低的净掺杂浓度。整流器还具有从第一面延伸到半导体区域中的多个沟槽; 所述沟槽限定所述半导体区域内的多个台面，并且所述沟槽形成多个沟槽交叉点。整流器还包括覆盖沟槽底部的半导体区域和沟槽侧壁的下部的氧化物层，设置在沟槽内的氧化物层上的多晶硅区域以及覆盖部分的沟槽交点处的绝缘区域的多晶硅区域和氧化物层的一部分。

48. 发明授权

US06420768B1 Trench schottky barrier rectifier and method of making the same 有权
标题翻译：沟槽肖特基势垒整流器及其制作方法
公开(公告)号：US06420768B1
公开(公告)日：2002-07-16
申请号：US09737357
申请日：2000-12-15
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L27095
CPC分类号： H01L29/66143 , H01L29/417 , H01L29/872
摘要： A trench Schottky barrier rectifier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.
摘要翻译：沟槽肖特基势垒整流器及其制造方法，其中整流器具有具有第一和第二相对面的半导体区域; 所述半导体区域具有与所述第一面相邻的第一导电类型的漂移区域和与所述第二面部相邻的所述第一导电类型的阴极区域; 漂移区具有比阴极区更低的净掺杂浓度。整流器还具有从第一面延伸到半导体区域中的多个沟槽; 所述沟槽限定所述半导体区域内的多个台面，并且所述沟槽形成多个沟槽交叉点。整流器还包括覆盖沟槽底部的半导体区域和沟槽的侧壁的下部的氧化物层，设置在沟槽内的氧化物层上的多晶硅区域以及覆盖部分的沟槽交点处的绝缘区域多晶硅区域和氧化物层的一部分。

49. 发明授权

US06376315B1 Method of forming a trench DMOS having reduced threshold voltage 有权
标题翻译：形成具有降低的阈值电压的沟槽DMOS的方法
公开(公告)号：US06376315B1
公开(公告)日：2002-04-23
申请号：US09540856
申请日：2000-03-31
申请人： Fwu-Iuan Hshieh , Koon Chong So
发明人： Fwu-Iuan Hshieh , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/1095
摘要： A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more or more body regions adjacent one or more trenches are provided. The one or more trenches are lined with a first insulating layer. A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions of the body regions. An oxide layer is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.
摘要翻译：提供制造一个或多个沟槽DMOS晶体管的方法。在该方法中，提供与一个或多个沟槽相邻的一个或多个或多个主体区域。一个或多个沟槽衬有第一绝缘层。第一绝缘层的一部分至少沿着沟槽的上侧壁去除，暴露身体区域的部分。然后在身体区域的至少暴露部分上形成氧化物层，导致与氧化物层相邻的体区内的载流子浓度降低的区域。体内区域中多数载流子浓度的这种修改是有利的，因为可以在DMOS晶体管内建立低阈值电压，而不需要使用更薄的栅极氧化物（这将降低产率和开关速度），而且基本上不增加冲击的可能性 -通过。

50. 发明授权

US5960275A Power MOSFET fabrication process to achieve enhanced ruggedness, cost savings, and product reliability 失效
标题翻译：功率MOSFET制造工艺，以实现增强的耐用性，成本节省和产品可靠性
公开(公告)号：US5960275A
公开(公告)日：1999-09-28
申请号：US738544
申请日：1996-10-28
申请人： Koon Chong So , Fwu-Iuan Hshieh
发明人： Koon Chong So , Fwu-Iuan Hshieh
IPC分类号： H01L21/336 , H01L29/10 , H01L21/8238
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/7811 , H01L29/0619 , H01L29/0638 , H01L29/402
摘要： This invention shows an improved method for fabricating a MOSFET transistor on a substrate to improve a device ruggedness. The method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and then growing an initial oxide layer over the epi-layer; (b) applying an active mask for etching the initial oxide layer to define an active area and forming a gate oxide layer thereon followed by depositing an overlaying polysilicon layer; (c) applying a poly mask for etching the polysilicon layer to define a plurality of poly gates; (d) removing the poly mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions and for growing a thin oxide layer overlaying the ploy gates and silicon surface; (e) depositing a blocking-and-alignment layer of dielectric material with a pre-designated thickness followed by implanting body-dopants of the second conductivity type at an energy level correlating to the thickness of the blocking-and-alignment layer to form a buried body-dopant region at a pre-determined depth in each of the body regions (f) removing the blocking-and-alignment layer followed by applying a source blocking mask for implanting a plurality of source regions in the body regions with ions of the first conductivity type followed by removing the source blocking mask; and (g) forming an insulation layer and applying a high temperature process for densification of the insulation layer and further for actuating a diffusion of the source regions and the deep heavily-doped body-dopant regions. The deep heavily-doped body-dopant regions are formed immediately below the source regions whereby the device ruggedness is improved.
摘要翻译：本发明示出了用于在衬底上制造MOSFET晶体管以改善器件耐用性的改进方法。该方法包括以下步骤：（a）在衬底上形成第一导电类型的外延层作为漏极区域，然后在外延层上生长初始氧化物层; （b）施加用于蚀刻初始氧化物层的活性掩模以限定有源区并在其上形成栅极氧化层，然后沉积覆盖多晶硅层; （c）施加多晶硅掩模以蚀刻多晶硅层以限定多个多晶硅栅极; （d）去除聚合物掩模，然后进行第二导电类型的体植入物，随后进行用于形成多个体区的体扩散，以及用于生长覆盖合金浇口和硅表面的薄氧化物层; （e）以预先指定的厚度沉积介电材料的阻挡和取向层，然后以与阻挡 - 取向层的厚度相关的能级注入第二导电类型的体掺杂物，以形成（f）中去除阻挡和取向层，然后施加源阻挡掩模，用于在身体区域中注入多个源区域，其中离子束第一导电类型，然后去除源阻挡掩模; 和（g）形成绝缘层并施加用于密封绝缘层的高温工艺，并且进一步用于致动源区域和深重掺杂体 - 掺杂区域的扩散。深度重掺杂的体 - 掺杂剂区域形成在源极区域的正下方，从而改善了器件的坚固性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式