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    • 42. 发明授权
    • Magnetic head and method of fabricating same
    • 磁头及其制造方法
    • US4559572A
    • 1985-12-17
    • US575704
    • 1984-01-31
    • Noriyuki KumasakaHideo FujiwaraShigekazu OtomoTakeo YamashitaShinji TakayamaNoritoshi SaitoNobuo KobayashiMitsuhiro Kudo
    • Noriyuki KumasakaHideo FujiwaraShigekazu OtomoTakeo YamashitaShinji TakayamaNoritoshi SaitoNobuo KobayashiMitsuhiro Kudo
    • G11B5/127G11B5/147G11B5/23G11B5/31G11B5/12
    • G11B5/147G11B5/3106
    • A magnetic head core and a method of fabricating same, wherein a magnetic circuit is constituted by a pair of magnetic films having a V-shaped cross section which face each other at each protrudent section through the gap material. The cross-sectional portion of the V-shaped film is exposed to the surface facing the magnetic recording medium. The protrusions of the magnetic film pair have tip planes parallel to each other and substantially perpendicular to the moving direction of the magnetic recording medium. The tip plane has a width defined by the line of intersection between the plane and the surface facing the magnetic recording medium in correspondence to the recording track width. At least one of the magnetic films has a window for winding an excitation coil. The magnetic film is formed on the non-magnetic protection member having a V-shaped protrusion. The magnetic head has superior recording and reproducing characteristics in a wide frequency band with less rubbing noise, high wear-resistivity and high productivity, and operates without the pseudo gap effect. The magnetic head core is fabricated through the steps of forming a coil winding groove in the gap forming plane of a non-magnetic core block, forming a number of parallel grooves perpendicularly to the winding groove so that a number of V-shaped protrusions are produced, forming a magnetic film on the surface of the protrusions, forming a gap plane after the magnetic film has been coated with non-magnetic material, and splitting the block and then combining the two core blocks to complete a magnetic head core.
    • 一种磁头芯及其制造方法,其中磁路由通过间隙材料的每个突出部分彼此面对的具有V形横截面的一对磁膜构成。 V形膜的横截面部分暴露于面向磁记录介质的表面。 磁性膜对的突起具有彼此平行的并且基本上垂直于磁记录介质的移动方向的尖端平面。 尖端平面具有与记录轨道宽度相对应的平面与面向磁记录介质的表面之间的交点线限定的宽度。 至少一个磁性膜具有用于缠绕励磁线圈的窗口。 磁性膜形成在具有V形突起的非磁性保护构件上。 磁头在宽频带具有优异的记录和再现特性,具有较少的摩擦噪声,高耐磨性和高生产率,并且没有伪间隙效应。 通过在非磁性芯块的间隙形成平面中形成线圈绕槽的步骤制造磁头芯,与绕组槽垂直地形成多个平行的沟槽,从而产生多个V形突起 在突起的表面上形成磁性膜,在磁性膜被非磁性材料涂覆之后形成间隙平面,分割该块,然后组合两个核心块,从而形成磁头芯。
    • 46. 发明授权
    • Front portion structure of vehicle
    • 车辆前部结构
    • US07735892B2
    • 2010-06-15
    • US12032493
    • 2008-02-15
    • Junichi SakamotoSadamichi EnjoHideo Fujiwara
    • Junichi SakamotoSadamichi EnjoHideo Fujiwara
    • B62H5/00
    • B62H5/00B62K19/40B62K2202/00G07C9/00182G07C2009/00793
    • A vehicle front portion structure having a storage portion for facilitating maintenance for a vehicle front portion includes a first storage portion that includes a bottom portion extending in the longitudinal direction of a vehicle body, left and right walls extending upwardly from the bottom portion, a ceiling portion connecting the left and right walls and a back wall closing the respective backs of the bottom portion, left and right walls and ceiling portion. The first storage portion is provided with a maintenance opening formed to be spanned among the back wall, a left wall continuous with the back wall and the bottom portion continuous with the back wall, and with the lid body which covers the maintenance opening in an attachable and detachable manner. A key cylinder arrangement structure for a vehicle is provided that can significantly enhance operability of a key cylinder while preventing tampering or theft.
    • 一种具有便于车辆前部保养的收纳部的车辆前部结构,包括:第一收纳部,其具有沿车体长度方向延伸的底部;从所述底部向上延伸的左右壁; 连接左壁和右壁的部分和封闭底部,左壁和右壁和顶部的相应后部的后壁。 第一存储部分设置有维护开口,其形成为跨越后壁,与后壁连续的左壁和与后壁连续的底部,以及具有可附接的维护开口的盖体 并可拆卸。 提供一种用于车辆的钥匙筒布置结构,其可以显着提高钥匙筒的可操作性,同时防止篡改或盗窃。
    • 49. 发明授权
    • Serial data detection circuit performing same offset adjustment to signal receiver as performed to reference receiver
    • 串行数据检测电路对参考接收机执行与信号接收机相同的偏移调整
    • US06781905B2
    • 2004-08-24
    • US10368878
    • 2003-02-19
    • Hideo Fujiwara
    • Hideo Fujiwara
    • G11C702
    • H04L25/062H03K5/082
    • A pair of serial data signals having reciprocal signal levels are detected when a voltage of one of the serial data signals becomes larger than a voltage of the other serial data signal that is provided with an offset by a differential amplification circuit included in a signal detection circuit unit. A differential amplification circuit unit provides an offset for one of different predetermined constant voltages supplied thereto, and outputs signals by performing a differential amplification to the different constant voltages. An offset control circuit unit controls the offset provided by the differential amplification circuit unit so that voltages of the signals output by the differential amplification circuit unit coincide, and correspondingly controls the offset provided by the differential amplification circuit included in the signal detection circuit unit.
    • 当一个串行数据信号的电压变得大于由包括在信号检测电路中的差分放大电路提供偏移的其它串行数据信号的电压时,检测到具有互信号电平的一对串行数据信号 单元。 差分放大电路单元为提供给其的不同预定恒定电压之一提供偏移,并且通过对不同的恒定电压执行差分放大来输出信号。 偏移控制电路单元控制由差分放大电路单元提供的偏移,使得由差分放大电路单元输出的信号的电压一致,并且相应地控制由包括在信号检测电路单元中的差分放大电路提供的偏移。
    • 50. 发明授权
    • Integrated circuit with design for testability and method for designing the same
    • 具有可测试性设计的集成电路及其设计方法
    • US06735730B1
    • 2004-05-11
    • US09699478
    • 2000-10-31
    • Hideo FujiwaraToshimitsu MasuzawaSatoshi Ohtake
    • Hideo FujiwaraToshimitsu MasuzawaSatoshi Ohtake
    • G01R3128
    • G01R31/3183G01R31/31724
    • A test controller 4 has a test plan generating unit 11 for generating a test plan of a data path 2 which is formed to have a fixed control testability in which a test plan constituted by three phases, that is, the propagation of a test vector to a data input, the execution of a test and the propagation of an output response is present for each test object module. Thus, an integrated circuit is capable of supplying a test plan as a time series of a control signal to a control input of a data path, shortening a test execution time and generating the test plan at the normal operation speed of the circuit, thereby carrying out a test at an actual operation speed and an integrated circuit designing method.
    • 测试控制器4具有测试计划生成单元11,用于生成数据路径2的测试计划,数据路径2形成为具有固定控制可测试性,其中由三个阶段构成的测试计划,即测试向量的传播到 对于每个测试对象模块,存在数据输入,测试的执行和输出响应的传播。 因此,集成电路能够将作为控制信号的时间序列的测试计划提供给数据路径的控制输入,缩短测试执行时间,并以电路的正常操作速度生成测试计划,从而携带 以实际运行速度进行测试和集成电路设计方法。