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41. 外观设计

USD490430S1 Keyboard 失效
公开(公告)号：USD490430S1
公开(公告)日：2004-05-25
申请号：US29173199
申请日：2002-12-26
申请人： Wen-Jer Tsai
设计人： Wen-Jer Tsai

42. 发明授权

US06512710B1 Reliability test method and circuit for non-volatile memory 有权
标题翻译：非易失性存储器的可靠性测试方法和电路
公开(公告)号：US06512710B1
公开(公告)日：2003-01-28
申请号：US10004636
申请日：2001-12-04
申请人： Wen-Jer Tsai , Lan Ting Huang , Nian-Kai Zous , Ta-Hui Wang
发明人： Wen-Jer Tsai , Lan Ting Huang , Nian-Kai Zous , Ta-Hui Wang
IPC分类号： G11C700
CPC分类号： G11C29/50016 , G11C8/08 , G11C16/04 , G11C29/50
摘要： A reliability test method for a non-volatile memory. A relation curve of gate voltage versus read current degradation rate is obtained. The read current degradation rate of an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding to the actual gate voltage are obtained. With the accelerated test gate voltage, the test is continuously performed within the test time. Afterward, a test result of the memory is then obtained and, by the result, it is judged whether the data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.
摘要翻译：用于非易失性存储器的可靠性测试方法。获得栅极电压与读取电流退化率的关系曲线。估计实际栅极电压的读取电流劣化率。从关系曲线可以得到与实际栅极电压对应的加速测试栅极电压和测试时间。加速测试门电压，测试在测试时间内连续进行。然后，获得存储器的测试结果，并且通过结果判断数据是否有效。如果数据正确（保留），则可以保证存储器具有预期的使用寿命; 如果数据错误（丢失），则存储器被判定为无法通过寿命测试。

43. 发明授权

US09209316B2 ROM for constraining 2nd-bit effect 有权
标题翻译： ROM限制第二位效果
公开(公告)号：US09209316B2
公开(公告)日：2015-12-08
申请号：US13421389
申请日：2012-03-15
申请人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L27/115 , H01L29/792 , G11C11/56 , G11C16/04
CPC分类号： H01L29/792 , G11C11/5621 , G11C16/0466 , H01L27/11521 , H01L27/11568
摘要： A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.
摘要翻译：提供了包括基板，源极区和漏极区，电荷存储结构，栅极和局部极化掺杂区域的只读存储器。源极区域和漏极区域设置在衬底中，电荷存储结构位于源极区域和漏极区域之间的衬底上，并且栅极被配置在电荷存储结构上。局部极掺杂区位于源区和漏区之间的衬底中，并且包括低掺杂浓度区和至少一个高掺杂浓度区。高掺杂浓度区域设置在低掺杂浓度区域和源极区域和漏极区域之一中，并且高掺杂浓度区域的掺杂浓度是低掺杂浓度的掺杂浓度的三倍或更多倍地区。

44. 发明授权

US07754544B2 Dynamic random access memory cell and manufacturing method thereof 有权
标题翻译：动态随机存取存储单元及其制造方法
公开(公告)号：US07754544B2
公开(公告)日：2010-07-13
申请号：US12570147
申请日：2009-09-30
申请人： Ta-Wei Lin , Wen-Jer Tsai
发明人： Ta-Wei Lin , Wen-Jer Tsai
IPC分类号： H01L21/8242
CPC分类号： H01L27/10802 , H01L21/84 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.
摘要翻译：提供了一种动态随机存取存储单元及其制造方法。首先，提供形成有底部氧化物层和半导体层的基板。半导体层形成在底部氧化物层上。接下来，在半导体层上形成栅极。然后，对半导体层进行图案化以暴露底部氧化物层的一部分。之后，在半导体层的侧壁形成绝缘层，其中绝缘层的高度比半导体层的高度短，从而在绝缘层的顶部和半导体层之间形成间隙。此外，在底部氧化物层上形成覆盖绝缘层并且与半导体层具有相同高度的掺杂层。掺杂层经由间隙与半导体层的侧壁接触。

45. 发明授权

US07031196B2 Nonvolatile semiconductor memory and operating method of the memory 有权
标题翻译：非易失性半导体存储器和存储器的操作方法
公开(公告)号：US07031196B2
公开(公告)日：2006-04-18
申请号：US10757073
申请日：2004-01-14
申请人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
发明人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
IPC分类号： G11C16/00
CPC分类号： G11C16/0475 , G11C16/3468 , H01L21/28273 , H01L29/792 , H01L29/7923
摘要： A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.
摘要翻译：一种对存储器单元进行编程的方法包括将存储单元设置为第一栅极阈值电压的初始状态，执行处理顺序，包括：在栅极与第一结区域之间施加电压偏置，使电孔朝向保持在捕获层中，并且评估响应于电压偏置产生的读取电流，以确定是否达到第二栅极阈值电压，其中第二栅极阈值电压低于第一栅极阈值电压。通过改变栅极和第一结区域之间的电压偏压的一个或多个时间直到达到第二栅极阈值电压并且存储器单元处于编程状态来重复处理顺序多次。

46. 发明授权

US06914819B2 Non-volatile flash memory 有权
标题翻译：非易失性闪存
公开(公告)号：US06914819B2
公开(公告)日：2005-07-05
申请号：US10653892
申请日：2003-09-04
申请人： Chih-Chieh Yeh , Hung-Yueh Chen , Wen-Jer Tsai , Tao-Cheng Lu
发明人： Chih-Chieh Yeh , Hung-Yueh Chen , Wen-Jer Tsai , Tao-Cheng Lu
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/26 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/26
摘要： A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.
摘要翻译：一种操作非易失性存储单元的方法，其中所述非易失性存储单元包括字线，第一位线和第二位线，所述方法包括对所述存储器单元进行编程，所述存储单元包括向所述存储单元施加高正偏压第一位线，对第二位线施加接地偏置，以及向字线施加高负偏压，其中带正电荷的空穴穿过介电层进入捕获层。

47. 发明授权

US06801453B2 Method and apparatus of a read scheme for non-volatile memory 有权
标题翻译：用于非易失性存储器的读取方案的方法和装置
公开(公告)号：US06801453B2
公开(公告)日：2004-10-05
申请号：US10112871
申请日：2002-04-02
申请人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
发明人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/26
摘要： A method of a read scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, a source, a drain and a gate above a channel separated by a nonconducting charge trapping material sandwiched between first and second insulating layers. The method applies a first positive drain-to-source bias, a second positive source-to-substrate bias, and a third positive gate-to-source bias to read the source-side charges trapped in the trapping material near the source side.
摘要翻译：一种用于非易失性存储单元的读取方案的方法。非易失性存储单元包括衬底，源极，漏极以及由夹在第一绝缘层和第二绝缘层之间的非导电电荷捕获材料隔开的沟道之上的栅极。该方法应用第一正的漏极 - 源极偏置，第二正的源极 - 衬底偏置和第三正向栅极 - 源偏置来读取在源极附近的捕获材料中的源极电荷。

48. 发明授权

US06657894B2 Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells 有权
标题翻译：用于编程虚拟接地非易失性存储单元阵列而不干扰相邻单元的装置和方法
公开(公告)号：US06657894B2
公开(公告)日：2003-12-02
申请号：US10112923
申请日：2002-03-29
申请人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
发明人： Chih-Chieh Yeh , Wen-Jer Tsai , Tao-Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C16/0491 , G11C16/12
摘要： A virtual ground nonvolatile memory cell array is formed by a plurality of adjacent nonvolatile memory cells arranged in rows and columns so as to form an array. Each of the nonvolatile memory cells is formed by an N channel MOSFET with a trapping layer formed between two isolating layers. In the erase state, the trapping layer stores an amount of electrons. A method for programming the virtual ground nonvolatile memory cell array is also disclosed. The potentials applied to the bitlines and wordlines in the array are preset to program nonvolatile memory cells and not to disturb cells adjacent to the nonvolatile memory cell to be programmed.
摘要翻译：由布置成行和列的多个相邻的非易失性存储单元形成虚拟非易失性存储单元阵列，以形成阵列。每个非易失性存储单元由具有在两个隔离层之间形成的捕获层的N沟道MOSFET形成。在擦除状态下，捕获层存储一定量的电子。还公开了一种用于编程虚拟接地非易失性存储单元阵列的方法。应用于阵列中的位线和字线的电位被预设为非易失性存储器单元，而不是干扰与待编程的非易失性存储器单元相邻的单元。

49. 发明授权

US06563752B2 Qualification test method and circuit for a non-volatile memory 有权
标题翻译：用于非易失性存储器的资格测试方法和电路
公开(公告)号：US06563752B2
公开(公告)日：2003-05-13
申请号：US09945289
申请日：2001-08-30
申请人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
发明人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
IPC分类号： G11C700
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/50
摘要： A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.
摘要翻译：用于非易失性存储器的资格测试方法包括确定编程电压与存储器单元的寿命之间的关系曲线。估计在预期寿命期内相对于存储器阵列的编程电压。根据该关系曲线计算加速试验电压和对应于在预期寿命中运行的编程电压的试验时间。在加速测试电压下进行测试时间。测试编程状态下的所有存储单元，以查看原始编程状态是否仍然保留。如果编程状态保持不变，则判断存储器阵列具有使用寿命。如果编程状态不存在，则判断存储器阵列没有寿命周期。

50. 发明授权

US08674424B2 Memory device with charge storage layers at the sidewalls of the gate and method for fabricating the same 有权
标题翻译：在门的侧壁处具有电荷存储层的存储器件及其制造方法
公开(公告)号：US08674424B2
公开(公告)日：2014-03-18
申请号：US13304378
申请日：2011-11-24
申请人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
发明人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/28273 , G11C16/0458 , H01L21/28282 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.
摘要翻译：描述了存储器件，包括衬底上的栅极，栅极和衬底之间的栅极电介质，以及两个电荷存储层。栅极的宽度大于栅极电介质的宽度，使得在栅极电介质的两侧以及栅极和衬底之间存在两个间隙。每个电荷存储层包括在一个间隙中的主体部分，与主体部分连接并从门的相应侧壁突出的第一延伸部分，以及连接到第一延伸部分并沿着侧壁延伸的第二延伸部分所述第一延伸部分的边缘从所述第二延伸部分的侧壁突出。

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