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1. 发明授权

US08791522B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US08791522B2
公开(公告)日：2014-07-29
申请号：US13271517
申请日：2011-10-12
申请人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.
摘要翻译：提供了一种非易失性存储器及其制造方法。具有突出部的第一氧化物层形成在基板上。在突起的两侧在衬底中形成一对掺杂区域。在突起的侧壁上形成一对电荷存储间隔物。在第一氧化物层和电荷存储间隔物上形成第二氧化物层。在第二氧化物层上形成导电层。

2. 发明申请

US20120326222A1 MEMORY STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：记忆结构及其制作方法
公开(公告)号：US20120326222A1
公开(公告)日：2012-12-27
申请号：US13166144
申请日：2011-06-22
申请人： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
发明人： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
摘要： A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.
摘要翻译：提供包括存储单元的存储器结构，并且存储单元包括以下元件。第一栅极设置在基板上。层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构。第一电荷存储结构和第二电荷存储结构中的至少一个包括物理分离的两个电荷存储单元。第一电介质层在堆叠结构的两侧设置在第一栅极上。第一源极和漏极以及第二源极和漏极设置在第一介电层上并位于沟道层的两侧。

3. 发明授权

US08796754B2 Multi level programmable memory structure with multiple charge storage structures and fabricating method thereof 有权
标题翻译：具有多个电荷存储结构的多级可编程存储器结构及其制造方法
公开(公告)号：US08796754B2
公开(公告)日：2014-08-05
申请号：US13166144
申请日：2011-06-22
申请人： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
发明人： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
IPC分类号： H01L29/792 , H01L21/336 , H01L27/115 , H01L29/788
CPC分类号： H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
摘要： A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.
摘要翻译：提供包括存储单元的存储器结构，并且存储单元包括以下元件。第一栅极设置在基板上。层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构。第一电荷存储结构和第二电荷存储结构中的至少一个包括物理分离的两个电荷存储单元。第一电介质层在堆叠结构的两侧设置在第一栅极上。第一源极和漏极以及第二源极和漏极设置在第一介电层上并位于沟道层的两侧。

4. 发明申请

US20130240975A1 ROM FOR CONSTRAINING 2nd-BIT EFFECT 有权
标题翻译：用于约束第二位影响的ROM
公开(公告)号：US20130240975A1
公开(公告)日：2013-09-19
申请号：US13421389
申请日：2012-03-15
申请人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C11/5621 , G11C16/0466 , H01L27/11521 , H01L27/11568
摘要： A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.
摘要翻译：提供了包括基板，源极区和漏极区，电荷存储结构，栅极和局部极化掺杂区域的只读存储器。源极区域和漏极区域设置在衬底中，电荷存储结构位于源极区域和漏极区域之间的衬底上，并且栅极被配置在电荷存储结构上。局部极掺杂区位于源区和漏区之间的衬底中，并且包括低掺杂浓度区和至少一个高掺杂浓度区。高掺杂浓度区域设置在低掺杂浓度区域和源极区域和漏极区域之一中，并且高掺杂浓度区域的掺杂浓度是低掺杂浓度的掺杂浓度的三倍或更多倍地区。

5. 发明申请

US20130092997A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20130092997A1
公开(公告)日：2013-04-18
申请号：US13271517
申请日：2011-10-12
申请人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.
摘要翻译：提供了一种非易失性存储器及其制造方法。具有突出部的第一氧化物层形成在基板上。在突起的两侧在衬底中形成一对掺杂区域。在突起的侧壁上形成一对电荷存储间隔物。在第一氧化物层和电荷存储间隔物上形成第二氧化物层。在第二氧化物层上形成导电层。

6. 发明授权

US09209316B2 ROM for constraining 2nd-bit effect 有权
标题翻译： ROM限制第二位效果
公开(公告)号：US09209316B2
公开(公告)日：2015-12-08
申请号：US13421389
申请日：2012-03-15
申请人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L27/115 , H01L29/792 , G11C11/56 , G11C16/04
CPC分类号： H01L29/792 , G11C11/5621 , G11C16/0466 , H01L27/11521 , H01L27/11568
摘要： A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.
摘要翻译：提供了包括基板，源极区和漏极区，电荷存储结构，栅极和局部极化掺杂区域的只读存储器。源极区域和漏极区域设置在衬底中，电荷存储结构位于源极区域和漏极区域之间的衬底上，并且栅极被配置在电荷存储结构上。局部极掺杂区位于源区和漏区之间的衬底中，并且包括低掺杂浓度区和至少一个高掺杂浓度区。高掺杂浓度区域设置在低掺杂浓度区域和源极区域和漏极区域之一中，并且高掺杂浓度区域的掺杂浓度是低掺杂浓度的掺杂浓度的三倍或更多倍地区。

7. 发明授权

US08674424B2 Memory device with charge storage layers at the sidewalls of the gate and method for fabricating the same 有权
标题翻译：在门的侧壁处具有电荷存储层的存储器件及其制造方法
公开(公告)号：US08674424B2
公开(公告)日：2014-03-18
申请号：US13304378
申请日：2011-11-24
申请人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
发明人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/28273 , G11C16/0458 , H01L21/28282 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.
摘要翻译：描述了存储器件，包括衬底上的栅极，栅极和衬底之间的栅极电介质，以及两个电荷存储层。栅极的宽度大于栅极电介质的宽度，使得在栅极电介质的两侧以及栅极和衬底之间存在两个间隙。每个电荷存储层包括在一个间隙中的主体部分，与主体部分连接并从门的相应侧壁突出的第一延伸部分，以及连接到第一延伸部分并沿着侧壁延伸的第二延伸部分所述第一延伸部分的边缘从所述第二延伸部分的侧壁突出。

8. 发明申请

US20130134497A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20130134497A1
公开(公告)日：2013-05-30
申请号：US13304378
申请日：2011-11-24
申请人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
发明人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , G11C16/0458 , H01L21/28282 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.
摘要翻译：描述了存储器件，包括衬底上的栅极，栅极和衬底之间的栅极电介质，以及两个电荷存储层。栅极的宽度大于栅极电介质的宽度，使得在栅极电介质的两侧以及栅极和衬底之间存在两个间隙。每个电荷存储层包括在一个间隙中的主体部分，与主体部分连接并从门的相应侧壁突出的第一延伸部分，以及连接到第一延伸部分并沿着侧壁延伸的第二延伸部分所述第一延伸部分的边缘从所述第二延伸部分的侧壁突出。

9. 发明申请

US20080047817A1 KEYBOARDS 有权
标题翻译：键盘
公开(公告)号：US20080047817A1
公开(公告)日：2008-02-28
申请号：US11840157
申请日：2007-08-16
申请人： Wen-Kuang Hou , Chih-Chieh Cheng
发明人： Wen-Kuang Hou , Chih-Chieh Cheng
IPC分类号： H01H1/10
CPC分类号： H01H13/705 , H01H2203/048 , H01H2221/044 , H01H2223/002 , H01H2225/01 , H01H2231/032
摘要： A keyboard. A membrane circuit board includes a plurality of switches. At least one keycap is disposed on the membrane circuit board and includes a plurality of activating pillars respectively corresponding to and separated from the switches. When the keycap is moved toward the membrane circuit board, one of the activating pillars compresses one of the switches, outputting a signal corresponding to the keycap.
摘要翻译：键盘。薄膜电路板包括多个开关。至少一个键帽设置在膜电路板上，并且包括分别对应于并且与开关分离的多个激活支柱。当键帽朝向膜电路板移动时，其中一个激活柱压缩其中一个开关，输出对应于键帽的信号。

10. 发明授权

US07427725B2 Keyboards 有权
标题翻译：键盘
公开(公告)号：US07427725B2
公开(公告)日：2008-09-23
申请号：US11840157
申请日：2007-08-16
申请人： Wen-Kuang Hou , Chih-Chieh Cheng
发明人： Wen-Kuang Hou , Chih-Chieh Cheng
IPC分类号： H01H13/70
CPC分类号： H01H13/705 , H01H2203/048 , H01H2221/044 , H01H2223/002 , H01H2225/01 , H01H2231/032
摘要： A keyboard. A membrane circuit board includes a plurality of switches. At least one keycap is disposed on the membrane circuit board and includes a plurality of activating pillars respectively corresponding to and separated from the switches. When the keycap is moved toward the membrane circuit board, one of the activating pillars compresses one of the switches, outputting a signal corresponding to the keycap.
摘要翻译：键盘。膜电路板包括多个开关。至少一个键帽设置在膜电路板上，并且包括分别对应于并且与开关分离的多个激活支柱。当键帽朝向膜电路板移动时，其中一个激活柱压缩其中一个开关，输出对应于键帽的信号。

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