专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08796754B2 Multi level programmable memory structure with multiple charge storage structures and fabricating method thereof 有权
标题翻译：具有多个电荷存储结构的多级可编程存储器结构及其制造方法
公开(公告)号：US08796754B2
公开(公告)日：2014-08-05
申请号：US13166144
申请日：2011-06-22
申请人： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
发明人： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
IPC分类号： H01L29/792 , H01L21/336 , H01L27/115 , H01L29/788
CPC分类号： H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
摘要： A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.
摘要翻译：提供包括存储单元的存储器结构，并且存储单元包括以下元件。第一栅极设置在基板上。层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构。第一电荷存储结构和第二电荷存储结构中的至少一个包括物理分离的两个电荷存储单元。第一电介质层在堆叠结构的两侧设置在第一栅极上。第一源极和漏极以及第二源极和漏极设置在第一介电层上并位于沟道层的两侧。

2. 发明授权

US08674424B2 Memory device with charge storage layers at the sidewalls of the gate and method for fabricating the same 有权
标题翻译：在门的侧壁处具有电荷存储层的存储器件及其制造方法
公开(公告)号：US08674424B2
公开(公告)日：2014-03-18
申请号：US13304378
申请日：2011-11-24
申请人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
发明人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/28273 , G11C16/0458 , H01L21/28282 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.
摘要翻译：描述了存储器件，包括衬底上的栅极，栅极和衬底之间的栅极电介质，以及两个电荷存储层。栅极的宽度大于栅极电介质的宽度，使得在栅极电介质的两侧以及栅极和衬底之间存在两个间隙。每个电荷存储层包括在一个间隙中的主体部分，与主体部分连接并从门的相应侧壁突出的第一延伸部分，以及连接到第一延伸部分并沿着侧壁延伸的第二延伸部分所述第一延伸部分的边缘从所述第二延伸部分的侧壁突出。

3. 发明授权

US08791522B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US08791522B2
公开(公告)日：2014-07-29
申请号：US13271517
申请日：2011-10-12
申请人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.
摘要翻译：提供了一种非易失性存储器及其制造方法。具有突出部的第一氧化物层形成在基板上。在突起的两侧在衬底中形成一对掺杂区域。在突起的侧壁上形成一对电荷存储间隔物。在第一氧化物层和电荷存储间隔物上形成第二氧化物层。在第二氧化物层上形成导电层。

4. 发明申请

US20120326222A1 MEMORY STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：记忆结构及其制作方法
公开(公告)号：US20120326222A1
公开(公告)日：2012-12-27
申请号：US13166144
申请日：2011-06-22
申请人： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
发明人： Cheng-Hsien Cheng , Wen-Jer Tsai , Shih-Guei Yan , Chih-Chieh Cheng , Jyun-Siang Huang
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
摘要： A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.
摘要翻译：提供包括存储单元的存储器结构，并且存储单元包括以下元件。第一栅极设置在基板上。层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构。第一电荷存储结构和第二电荷存储结构中的至少一个包括物理分离的两个电荷存储单元。第一电介质层在堆叠结构的两侧设置在第一栅极上。第一源极和漏极以及第二源极和漏极设置在第一介电层上并位于沟道层的两侧。

5. 发明申请

US20130134497A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20130134497A1
公开(公告)日：2013-05-30
申请号：US13304378
申请日：2011-11-24
申请人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
发明人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , G11C16/0458 , H01L21/28282 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.
摘要翻译：描述了存储器件，包括衬底上的栅极，栅极和衬底之间的栅极电介质，以及两个电荷存储层。栅极的宽度大于栅极电介质的宽度，使得在栅极电介质的两侧以及栅极和衬底之间存在两个间隙。每个电荷存储层包括在一个间隙中的主体部分，与主体部分连接并从门的相应侧壁突出的第一延伸部分，以及连接到第一延伸部分并沿着侧壁延伸的第二延伸部分所述第一延伸部分的边缘从所述第二延伸部分的侧壁突出。

6. 发明申请

US20130092997A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20130092997A1
公开(公告)日：2013-04-18
申请号：US13271517
申请日：2011-10-12
申请人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.
摘要翻译：提供了一种非易失性存储器及其制造方法。具有突出部的第一氧化物层形成在基板上。在突起的两侧在衬底中形成一对掺杂区域。在突起的侧壁上形成一对电荷存储间隔物。在第一氧化物层和电荷存储间隔物上形成第二氧化物层。在第二氧化物层上形成导电层。

7. 发明授权

US08698222B2 Memory device with charge storage layers at the gaps located both sides of the gate dielectric underneath the gate 有权
标题翻译：在位于栅极下方的栅极电介质的两侧的间隙处具有电荷存储层的存储器件
公开(公告)号：US08698222B2
公开(公告)日：2014-04-15
申请号：US13304380
申请日：2011-11-24
申请人： Shih-Guei Yan , Wen-Jer Tsai , Cheng-Hsien Cheng
发明人： Shih-Guei Yan , Wen-Jer Tsai , Cheng-Hsien Cheng
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7881 , H01L29/792
摘要： A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate.
摘要翻译：描述了存储器件，包括衬底上的隧道介电层，隧道介电层上的栅极，栅极和隧道介电层之间的至少一个电荷存储层，栅极旁边的衬底中的两个掺杂区域，以及字线，其设置在栅极上并电连接到栅极并且具有大于栅极的厚度的厚度。

8. 发明授权

US08664709B2 Non-volatile memory and fabricating method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US08664709B2
公开(公告)日：2014-03-04
申请号：US12839559
申请日：2010-07-20
申请人： Shih-Guei Yan , Wen-Jer Tsai , Jyun-Siang Huang
发明人： Shih-Guei Yan , Wen-Jer Tsai , Jyun-Siang Huang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions.
摘要翻译：提供包括衬底，堆叠栅极结构，两个掺杂区域和多个间隔物的非易失性存储器。堆叠的栅极结构设置在衬底上，其中堆叠的栅极结构包括从底部到顶部相对于衬底的顺序的第一介电层，电荷存储层，第二介电层和导电层。掺杂区域分别设置在堆叠栅极结构的两侧的衬底中，并且掺杂区域的底部部分在掺杂区域下与衬底接触。间隔物分别设置在每个掺杂区域和衬底的每一侧之间，并且间隔物的顶部部分低于掺杂区域的顶部部分。

9. 发明申请

US20130134498A1 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20130134498A1
公开(公告)日：2013-05-30
申请号：US13304380
申请日：2011-11-24
申请人： Shih-Guei Yan , Wen-Jer Tsai , Cheng-Hsien Cheng
发明人： Shih-Guei Yan , Wen-Jer Tsai , Cheng-Hsien Cheng
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7881 , H01L29/792
摘要： A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate.
摘要翻译：描述了存储器件，包括衬底上的隧道介电层，隧道介电层上的栅极，栅极和隧道介电层之间的至少一个电荷存储层，栅极旁边的衬底中的两个掺杂区域，以及字线，其设置在栅极上并电连接到栅极并且具有大于栅极的厚度的厚度。

10. 发明申请

US20130105882A1 MEMORY STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：记忆结构及其制作方法
公开(公告)号：US20130105882A1
公开(公告)日：2013-05-02
申请号：US13287728
申请日：2011-11-02
申请人： Jyun-Siang Huang , Wen-Jer Tsai , Shih-Guei Yan
发明人： Jyun-Siang Huang , Wen-Jer Tsai , Shih-Guei Yan
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42332 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory structure having a memory cell including a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer is provided. The first dielectric layer is on the substrate. The gate includes a base portion on the first dielectric layer and a protruding portion disposed on the base portion and partially exposing the base portion. The semiconductor layer is conformally disposed on the gate, and includes a top portion over the protruding portion, a bottom portion over the base portion exposed by the protruding portion and a side portion located at a sidewall of the protruding portion and connecting the top and bottom portions. The first and second doped regions are respectively in the top and bottom portions. The side portion serves as a channel region. The charge storage layer is between the gate and the semiconductor layer.
摘要翻译：提供了具有包括第一介电层，栅极，半导体层，第一掺杂区域，第二掺杂区域和电荷存储层的存储单元的存储器结构。第一介电层位于基板上。所述栅极包括在所述第一介电层上的基部和设置在所述基部上的部分露出所述基部的突出部。所述半导体层保形地设置在所述栅极上，并且包括在所述突出部分之上的顶部，所述基部上的由所述突出部分露出的底部和位于所述突出部分的侧壁处的侧部，并且将所述顶部和底部部分。第一和第二掺杂区分别位于顶部和底部。侧部用作沟道区域。电荷存储层位于栅极和半导体层之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式