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1. 发明授权

US07243277B2 Method of combining multilevel memory cells for an error correction scheme 有权
标题翻译：组合用于纠错方案的多电平存储器单元的方法
公开(公告)号：US07243277B2
公开(公告)日：2007-07-10
申请号：US11183601
申请日：2005-07-18
申请人： Jieh-Tsorng Wu , Ta-Hui Wang , Hsie-Chia Chang
发明人： Jieh-Tsorng Wu , Ta-Hui Wang , Hsie-Chia Chang
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/00 , G11C29/42
摘要： A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.
摘要翻译：存储器组合用于存储数据的多个存储单元，其中存储单元的差分级电压电平不受2的平方值的限制，并且可以线性地改善。本发明的特征还可以增加存储容量而不增加存储区。此外，当读取数据时，它可以保持不能表示错误消除消息的0和1组合的电压电平。为了有效利用存储器，增加的存储器容量不仅用于存储数据，而且用于存储纠错方案以确保存储数据的真实性，并提高多级存储器系统的产量和可靠性。

2. 发明申请

US20060015793A1 Method of combining multilevel memory cells for an error correction scheme 有权
标题翻译：组合用于纠错方案的多电平存储器单元的方法
公开(公告)号：US20060015793A1
公开(公告)日：2006-01-19
申请号：US11183601
申请日：2005-07-18
申请人： Jieh-Tsorng Wu , Ta-Hui Wang , Hsie-Chia Chang
发明人： Jieh-Tsorng Wu , Ta-Hui Wang , Hsie-Chia Chang
IPC分类号： H03M13/00
CPC分类号： G11C29/44 , G11C29/00 , G11C29/42
摘要： A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.
摘要翻译：存储器组合用于存储数据的多个存储单元，其中存储单元的差分级电压电平不受2的平方值的限制，并且可以线性地改善。本发明的特征还可以增加存储容量而不增加存储区。此外，当读取数据时，它可以保持不能表示错误消除消息的0和1组合的电压电平。为了有效利用存储器，增加的存储器容量不仅用于存储数据，而且用于存储纠错方案以确保存储数据的真实性，并提高多级存储器系统的产量和可靠性。

3. 发明授权

US06552921B2 Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory 有权
标题翻译：电路模拟铁电存储器的极化弛豫现象
公开(公告)号：US06552921B2
公开(公告)日：2003-04-22
申请号：US10050075
申请日：2002-01-15
申请人： Ching-Wei Tsai , Shyue-Yi Lee , Ta-Hui Wang
发明人： Ching-Wei Tsai , Shyue-Yi Lee , Ta-Hui Wang
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit has a MOS transistor, a ferroelectric capacitor, a capacitor, and a relaxation voltage source. The gate of the MOS transistor is coupled to a word line and the source of the MOS transistor is coupled to a bit line. A first electrode of the ferroelectric capacitor is coupled to the drain of the MOS transistor and the second electrode of the ferroelectric capacitor is coupled to a plate line. A first electrode of the capacitor is coupled to the drain of the MOS transistor. A first electrode of the relaxation voltage source is coupled to the second electrode of the capacitor, and the second electrode of the relaxation voltage source is coupled to a ground. The capacitance of the capacitor mentioned above is selectively far smaller than the capacitance of the bit line.
摘要翻译：一种用于模拟铁电存储器的偏振弛豫现象的电路。该电路具有MOS晶体管，铁电电容器，电容器和松弛电压源。 MOS晶体管的栅极耦合到字线，并且MOS晶体管的源极耦合到位线。铁电电容器的第一电极耦合到MOS晶体管的漏极，并且铁电电容器的第二电极耦合到板线。电容器的第一电极耦合到MOS晶体管的漏极。松弛电压源的第一电极耦合到电容器的第二电极，并且弛豫电压源的第二电极耦合到地。上述电容器的电容选择性地远小于位线的电容。

4. 发明授权

US06445614B1 Accelerated testing method and circuit for non-volatile memory 有权
标题翻译：非易失性存储器的加速测试方法和电路
公开(公告)号：US06445614B1
公开(公告)日：2002-09-03
申请号：US09930745
申请日：2001-08-14
申请人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
发明人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/50 , G11C2029/1202
摘要： An accelerated test for a non-volatile memory. A threshold voltage variation standard for assessment is selected. A set of negative gate bias voltages is applied to the gate terminals of the non-volatile memory to conduct the accelerated testing and obtain a test result. A curve relating lifetime and negative gate bias voltage is derived from the test result. According to the threshold voltage variation standard, the lifetime of the non-volatile memory is found. A word line negative gate bias voltage generator is coupled to a word line driver to apply a set of negative gate bias voltages to the gate terminals of programmed memory cells and conduct an accelerated testing.
摘要翻译：非易失性存储器的加速测试。选择用于评估的阈值电压变化标准。一组负栅极偏置电压施加到非易失性存储器的栅极端子，以进行加速测试并获得测试结果。从测试结果得出相关寿命和负栅极偏置电压的曲线。根据阈值电压变化标准，找到非易失性存储器的寿命。字线负栅极偏置电压发生器耦合到字线驱动器以将一组负栅极偏置电压施加到编程的存储器单元的栅极端子并进行加速测试。

5. 发明申请

US20090116294A1 METHOD OF PROGRAMMING CELL IN MEMORY AND MEMORY APPARATUS UTILIZING THE METHOD 有权
标题翻译：在存储器中编程单元的方法和利用该方法的存储器件
公开(公告)号：US20090116294A1
公开(公告)日：2009-05-07
申请号：US12138707
申请日：2008-06-13
申请人： Wen-Jer Tsai , Ta-Hui Wang , Chih-Wei Lee
发明人： Wen-Jer Tsai , Ta-Hui Wang , Chih-Wei Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/ID region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.
摘要翻译：一种对存储器中的第一单元进行编程的方法，其中所述第一单元具有第一S / D区域并与具有与所述第二S / D区域相反的第三S / D区域的第二单元共享第二S / D区域。第一单元和第二单元的通道导通，第一电压施加到第一S / D区，第二电压施加到第二S / D区，第三电压施加到第三S / D区地区。第二电压在第一电压和第三电压之间，第一至第三电压使载流子从第三S / D区流向第一S / ID区，并使第一电池的通道中的热载流子注入进入第一电池的电荷存储层。

6. 发明授权

US06563752B2 Qualification test method and circuit for a non-volatile memory 有权
标题翻译：用于非易失性存储器的资格测试方法和电路
公开(公告)号：US06563752B2
公开(公告)日：2003-05-13
申请号：US09945289
申请日：2001-08-30
申请人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
发明人： Wen-Jer Tsai , Nian-Kai Zous , Ta-Hui Wang
IPC分类号： G11C700
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/50
摘要： A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.
摘要翻译：用于非易失性存储器的资格测试方法包括确定编程电压与存储器单元的寿命之间的关系曲线。估计在预期寿命期内相对于存储器阵列的编程电压。根据该关系曲线计算加速试验电压和对应于在预期寿命中运行的编程电压的试验时间。在加速测试电压下进行测试时间。测试编程状态下的所有存储单元，以查看原始编程状态是否仍然保留。如果编程状态保持不变，则判断存储器阵列具有使用寿命。如果编程状态不存在，则判断存储器阵列没有寿命周期。

7. 发明授权

US07916551B2 Method of programming cell in memory and memory apparatus utilizing the method 有权
标题翻译：利用该方法在存储器和存储装置中编程单元的方法
公开(公告)号：US07916551B2
公开(公告)日：2011-03-29
申请号：US12138707
申请日：2008-06-13
申请人： Wen-Jer Tsai , Ta-Hui Wang , Chih-Wei Lee
发明人： Wen-Jer Tsai , Ta-Hui Wang , Chih-Wei Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/D region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.
摘要翻译：一种对存储器中的第一单元进行编程的方法，其中所述第一单元具有第一S / D区域并与具有与所述第二S / D区域相反的第三S / D区域的第二单元共享第二S / D区域。第一单元和第二单元的通道导通，第一电压施加到第一S / D区，第二电压施加到第二S / D区，第三电压施加到第三S / D区地区。第二电压在第一电压和第三电压之间，并且第一至第三电压使载流子从第三S / D区流向第一S / D区，并使第一电池的通道中的热载流子注入进入第一电池的电荷存储层。

8. 发明授权

US06512710B1 Reliability test method and circuit for non-volatile memory 有权
标题翻译：非易失性存储器的可靠性测试方法和电路
公开(公告)号：US06512710B1
公开(公告)日：2003-01-28
申请号：US10004636
申请日：2001-12-04
申请人： Wen-Jer Tsai , Lan Ting Huang , Nian-Kai Zous , Ta-Hui Wang
发明人： Wen-Jer Tsai , Lan Ting Huang , Nian-Kai Zous , Ta-Hui Wang
IPC分类号： G11C700
CPC分类号： G11C29/50016 , G11C8/08 , G11C16/04 , G11C29/50
摘要： A reliability test method for a non-volatile memory. A relation curve of gate voltage versus read current degradation rate is obtained. The read current degradation rate of an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding to the actual gate voltage are obtained. With the accelerated test gate voltage, the test is continuously performed within the test time. Afterward, a test result of the memory is then obtained and, by the result, it is judged whether the data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.
摘要翻译：用于非易失性存储器的可靠性测试方法。获得栅极电压与读取电流退化率的关系曲线。估计实际栅极电压的读取电流劣化率。从关系曲线可以得到与实际栅极电压对应的加速测试栅极电压和测试时间。加速测试门电压，测试在测试时间内连续进行。然后，获得存储器的测试结果，并且通过结果判断数据是否有效。如果数据正确（保留），则可以保证存储器具有预期的使用寿命; 如果数据错误（丢失），则存储器被判定为无法通过寿命测试。

9. 发明授权

US06512696B1 Method of programming and erasing a SNNNS type non-volatile memory cell 有权
标题翻译：编程和擦除SNNNS型非易失性存储单元的方法
公开(公告)号：US06512696B1
公开(公告)日：2003-01-28
申请号：US09986932
申请日：2001-11-13
申请人： Tso-Hung Fan , Tao-Cheng Lu , Samuel Pan , Ta-Hui Wang
发明人： Tso-Hung Fan , Tao-Cheng Lu , Samuel Pan , Ta-Hui Wang
IPC分类号： G11C1604
CPC分类号： G11C16/12 , G11C16/14
摘要： A method of programming and erasing a SNNNS type non-volatile memory cell is provided. The programming operation is performed by channel hot electron injection from a drain side to an intermediate silicon nitride layer. The erasing operation is performed by channel hot hole injection from a drain side to an intermediate silicon nitride layer. The SNNNS type non-volatile memory cell provides highly efficient hot carrier injection under low applied voltages, both for programming and erasing operations. Thus, the present method provides improved performance characteristics such as shorter programming/erasing times and lower applied voltages.
摘要翻译：提供了一种编程和擦除SNNNS型非易失性存储单元的方法。通过从漏极侧到中间氮化硅层的通道热电子注入来进行编程动作。擦除操作通过从漏极侧到中间氮化硅层的通道热空穴注入来进行。 SNNNS型非易失性存储单元在低施加电压下提供高效率的热载流子注入，用于编程和擦除操作。因此，本方法提供改进的性能特征，例如较短的编程/擦除时间和较低的施加电压。

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