专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US5191241A Programmable interconnect architecture 失效
标题翻译：可编程互连体系结构
公开(公告)号：US5191241A
公开(公告)日：1993-03-02
申请号：US899729
申请日：1992-06-17
申请人： John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
发明人： John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
IPC分类号： H01L23/525 , H01L23/528
CPC分类号： H01L23/5252 , H01L23/528 , H01L2924/0002
摘要： A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.
摘要翻译：用户可配置电路架构包括布置在半导体衬底内的功能电路模块的二维阵列。设置在半导体衬底上方并与半导体衬底绝缘的第一互连层包含多个导体并且用于功能电路模块内的内部连接。设置在第一互连层之上并与第一互连层绝缘的第二互连层包含沿第一方向运行的多个导体的导体轨道，并用于互连功能电路模块的输入和输出。设置在第二互连层之上并与第二互连层绝缘的第三互连层包含沿第二方向延伸的导体的多个分段轨迹，导体中的一些导体与第二互连层中的导体中的一个段形成相交;以及用于互连功能电路模块输入和输出以实现所需的应用。多个用户可配置的互连元件直接放置在第二和第三互连层中的分段导体的选定段的交叉处的第二和第三互连层之间。更多用户可配置的互连元件位于第二和第三互连层中的分段导体的相邻段之间。位于功能电路模块之间的半导体衬底中的通过晶体管连接在第二和第三互连层中的相邻段之间以及第二和第三互连层中的选定交叉段之间。

42. 发明授权

US5070384A Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer 失效
标题翻译：引入电介质和非晶硅层的电可编程抗体元件
公开(公告)号：US5070384A
公开(公告)日：1991-12-03
申请号：US508306
申请日：1990-04-12
申请人： John L. McCollum , Shih-Ou Chen
发明人： John L. McCollum , Shih-Ou Chen
IPC分类号： H01L27/10 , H01L21/8247 , H01L23/525 , H01L23/532 , H01L27/115
CPC分类号： H01L23/5252 , H01L23/53223 , H01L2924/0002 , H01L2924/3011
摘要： An electrically programmable antifuse element incorporates a composite interlayer of dielectric material and amorphous silicon interposed between two electrodes. The lower electrode may be formed from a refractory metal such as tungsten. Preferably, a thin layer of titanium is deposited over the tungsten layer and its surface is then oxidized to form a thin layer of titanium oxide which serves as the dielectric material of the composite dielectric/amorphous silicon interlayer. A layer of amorphous silicon is then deposited on top of the titanium oxide dielectric to complete the formation of the composite interlayer. A topmost layer of a refractory metal such as tungsten is then applied over the amorphous silicon to form the topmost electrode of the antifuse.

43. 发明授权

US5057451A Method of forming an antifuse element with substantially reduced capacitance using the LOCOS technique 失效
标题翻译：使用LOCOS技术形成具有显着降低电容的抗体元件的方法
公开(公告)号：US5057451A
公开(公告)日：1991-10-15
申请号：US508303
申请日：1990-04-12
申请人： John L. McCollum
发明人： John L. McCollum
IPC分类号： H01L27/10 , H01L23/522 , H01L23/525
CPC分类号： H01L23/5252 , H01L23/5222 , H01L2924/0002 , H01L2924/3011 , Y10S148/014 , Y10S148/055 , Y10S148/116 , Y10S148/117 , Y10S148/141 , Y10S438/911 , Y10S438/981
摘要： A minimum sized aperture for a reduced capacitance anti-fuse or other structure may be formed by birds beak encroachment of thick oxide under a masking layer or by isotropic etching of a masking layer followed by birds beak encroachment of thick oxide.

44. 发明授权

US4876220A Method of making programmable low impedance interconnect diode element 失效
标题翻译：制造可编程低阻抗互连二极管元件的方法
公开(公告)号：US4876220A
公开(公告)日：1989-10-24
申请号：US104404
申请日：1987-11-13
申请人： Amr M. Mohsen , Esmat Z. Hamdy , John L. McCollum
发明人： Amr M. Mohsen , Esmat Z. Hamdy , John L. McCollum
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L23/5252 , H01L21/76886 , H01L2924/0002 , H01L2924/3011
摘要： A programmable low impedance interconnect diode element is disclosed having a lower electrode formed of a semiconductor material of a first conductivity type covered by an insulating dielectric layer which may be in a preferred embodiment comprised of an initial layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, covered by a layer of semiconductor material of a second conductivity type.A programmable read only memory array and a programmable logic array comprising a plurality of the above-described cells are also disclosed.
摘要翻译：公开了一种可编程的低阻抗互连二极管元件，其具有由绝缘介电层覆盖的第一导电类型的半导体材料形成的下电极，该绝缘介电层可以在优选实施例中包括二氧化硅的初始层，第二层硅氮化物和由第二导电类型的半导体材料层覆盖的第三层二氧化硅。还公开了一种可编程只读存储器阵列和包括多个上述单元的可编程逻辑阵列。

45. 发明授权

US4352236A Double field oxidation process 失效
标题翻译：双场氧化工艺
公开(公告)号：US4352236A
公开(公告)日：1982-10-05
申请号：US286578
申请日：1981-07-24
申请人： John L. McCollum
发明人： John L. McCollum
IPC分类号： H01L27/10 , H01L21/82 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L21/22
CPC分类号： H01L27/10844 , H01L21/82 , Y10S438/981
摘要： A process for growing field oxide particularly for a dynamic memory is described. The process results in thinner field oxides in the storage array (2000-3000 A) and thicker oxides for the peripheral circuits (7000-8000 A). The thinner field oxide regions have smaller bird-beaks, reducing required substrate area. The plate for the storage nodes are coupled to ground potential, thus the thinner field oxides in the storage region provide sufficient isolation.
摘要翻译：描述了特别用于动态存储器的生长场氧化物的方法。该过程导致存储阵列（2000-3000A）中较薄的场氧化物和外围电路（7000-8000A）的较厚氧化物。更薄的场氧化物区域具有较小的鸟嘴，减少了所需的衬底面积。用于存储节点的板耦合到地电位，因此存储区域中较薄的场氧化物提供足够的隔离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式