专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5191241A Programmable interconnect architecture 失效
标题翻译：可编程互连体系结构
公开(公告)号：US5191241A
公开(公告)日：1993-03-02
申请号：US899729
申请日：1992-06-17
申请人： John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
发明人： John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
IPC分类号： H01L23/525 , H01L23/528
CPC分类号： H01L23/5252 , H01L23/528 , H01L2924/0002
摘要： A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.
摘要翻译：用户可配置电路架构包括布置在半导体衬底内的功能电路模块的二维阵列。设置在半导体衬底上方并与半导体衬底绝缘的第一互连层包含多个导体并且用于功能电路模块内的内部连接。设置在第一互连层之上并与第一互连层绝缘的第二互连层包含沿第一方向运行的多个导体的导体轨道，并用于互连功能电路模块的输入和输出。设置在第二互连层之上并与第二互连层绝缘的第三互连层包含沿第二方向延伸的导体的多个分段轨迹，导体中的一些导体与第二互连层中的导体中的一个段形成相交;以及用于互连功能电路模块输入和输出以实现所需的应用。多个用户可配置的互连元件直接放置在第二和第三互连层中的分段导体的选定段的交叉处的第二和第三互连层之间。更多用户可配置的互连元件位于第二和第三互连层中的分段导体的相邻段之间。位于功能电路模块之间的半导体衬底中的通过晶体管连接在第二和第三互连层中的相邻段之间以及第二和第三互连层中的选定交叉段之间。

2. 发明授权

US5132571A Programmable interconnect architecture having interconnects disposed above function modules 失效
标题翻译：具有处于上述功能模块的互连的可编程互连架构
公开(公告)号：US5132571A
公开(公告)日：1992-07-21
申请号：US561110
申请日：1990-08-01
申请人： John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
发明人： John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
IPC分类号： H01L21/82 , H01L23/525 , H01L23/528 , H03K19/177
CPC分类号： H01L23/5252 , H01L23/528 , H01L2924/0002
摘要： A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second the third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

3. 发明授权

US4873459A Programmable interconnect architecture 失效
标题翻译：可编程互连体系结构
公开(公告)号：US4873459A
公开(公告)日：1989-10-10
申请号：US195728
申请日：1988-05-18
申请人： Abbas A. El Gamal , Khaled A. El-Ayat , Jonathan W. Greene , Ta-Pen R. Guo , Justin M. Reyneri
发明人： Abbas A. El Gamal , Khaled A. El-Ayat , Jonathan W. Greene , Ta-Pen R. Guo , Justin M. Reyneri
IPC分类号： G01R31/3185 , H03K19/177
CPC分类号： H03K19/17748 , G01R31/318516 , H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/17796
摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segements connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conducive to custom circuit design.
摘要翻译：公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。布线通道包括通过常开的可编程元件连接的布线段，位于要连接的任何两个段的交点处。可以包括感应电路和接线，以允许来自外部接口接口的内部电路节点（如模块输出）的100％可观察性。通用功能模块可以被配置为实现流行的逻辑功能并且具有有利于定制电路设计的物理布局。

4. 发明授权

US5172014A Programmable interconnect architecture 失效
标题翻译：可编程互连体系结构
公开(公告)号：US5172014A
公开(公告)日：1992-12-15
申请号：US621452
申请日：1991-01-15
申请人： Khaled El Ayat , Abbas A. El Gamal , Amr M. Mohsen
发明人： Khaled El Ayat , Abbas A. El Gamal , Amr M. Mohsen
IPC分类号： G01R31/3185 , H03K19/177
CPC分类号： H03K19/17736 , G01R31/318516 , H03K19/17704
摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected.
摘要翻译：公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。布线通道包括通过常开的可编程元件连接的布线段，所述可编程元件位于要连接的任何两个段的交点处。

5. 发明授权

US5073729A Segmented routing architecture 失效
标题翻译： SEGMENTED路由架构
公开(公告)号：US5073729A
公开(公告)日：1991-12-17
申请号：US542722
申请日：1990-06-22
申请人： Johathan W. Greene , Abbas A. El Gamal , Sinan Kaptanoglu
发明人： Johathan W. Greene , Abbas A. El Gamal , Sinan Kaptanoglu
IPC分类号： H01L21/82 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , G06F17/5077 , H03K19/17704
摘要： A segmented routing architecture includes three or more different interior segment lengths within all of the segmented tracks in a channel. Four or more different segment lengths of interior segments are present in a channel if the sole segment in each unsegmented track is considered, too. Two or more different segment lengths of interior segments exist within a single wiring track. Lengths of adjacent segments within a track are balanced with a ratio not exceeding about two. In any given channel, the average length of all the segments in each column is relatively low in the interior and increases substantially monotonically towards the ends of the channel.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式