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41. 发明申请

US20080247229A1 NON-VOLATILE STORAGE USING CURRENT SENSING WITH BIASING OF SOURCE AND P-Well 有权
标题翻译：使用电流传感与源极和P阱的非挥发性储存
公开(公告)号：US20080247229A1
公开(公告)日：2008-10-09
申请号：US11771997
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.
摘要翻译：一种非易失性存储装置，其中对非易失性存储元件执行电流检测。对第一非易失性存储元件的选定字线施加电压，并且将源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压在相应的正直流电平下被调节，以避免地电压或电压波动，如果源电压至少在接地电压下被调节，则会发生接地反弹或电压波动。通过感测非易失性存储元件的NAND串中的电流来确定非易失性存储元件的编程条件。感觉可以快速发生，因为等待地面反弹稳定没有延迟。

42. 发明申请

US20080158973A1 COMPLETE WORD LINE LOOK AHEAD WITH EFFICIENT DATA LATCH ASSIGNMENT IN NON-VOLATILE MEMORY READ OPERATIONS 有权
标题翻译：完整的字线前瞻性，无损数据分配在非易失性存储器读操作
公开(公告)号：US20080158973A1
公开(公告)日：2008-07-03
申请号：US11617544
申请日：2006-12-28
申请人： Man Lung Mui , Seungpil Lee
发明人： Man Lung Mui , Seungpil Lee
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C16/3418
摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.
摘要翻译：由于基于相邻单元存储的电荷的电场耦合，可能会发生存储在非易失性存储单元中的诸如浮动栅极之类的电荷存储区域的视在电荷的变化。为了解释这种偏差，在阅读时应用补偿。当读取所选择的字线时，首先读取相邻的字线，并且将数据存储在每个位线的一组数据锁存器中。每个位线的一个锁存器存储数据来自相邻字线的指示。然后基于相邻字线上的单元格的不同状态，利用补偿来读取所选择的字线。每个感测模块使用来自相邻字线的数据来选择感测结果，并对其位线进行适当的补偿。来自相邻字线的数据在适当的时间用来自所选择的字线的数据被覆盖，并且指示被更新以反映锁存器存储来自所选字线的数据。数据锁存器的有效使用消除了分离锁存器来存储来自相邻字线的数据的需要。

43. 发明授权

US08842471B2 Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: program to verify transition 有权
标题翻译：通过在NAND闪存的写操作期间均衡和调节源，阱和位线电平进行充电循环：程序验证转换
公开(公告)号：US08842471B2
公开(公告)日：2014-09-23
申请号：US13570746
申请日：2012-08-09
申请人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Masahide Matsumoto , Jongmin Park , Man Lung Mui , Sung-En Wang
发明人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Masahide Matsumoto , Jongmin Park , Man Lung Mui , Sung-En Wang
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
摘要翻译：在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。考虑脉冲和验证阶段之间的间隔。对于脉冲之后的间隔，但是在建立验证条件之前，可以将源极，位线以及可能的阱电平相等化，然后在期望的DC电平进行调节。在验证阶段之后，但是在将存储器应用于下一个脉冲之前，源和位线电平可以均衡为直流电平。

44. 发明申请

US20130176790A1 Charge Cycling By Equalizing the Source and Bit Line Levels Between Pulses During No-Verify Write Operations for NAND Flash Memory 有权
标题翻译：通过在NAND闪存的无验证写入操作期间均衡脉冲之间的源和位线电平来进行充电循环
公开(公告)号：US20130176790A1
公开(公告)日：2013-07-11
申请号：US13570826
申请日：2012-08-09
申请人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Jungmin Park , Man Lung Mui
发明人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Jungmin Park , Man Lung Mui
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.
摘要翻译：在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。在一些情况下，非易失性存储器通过交替的脉冲组编程，但对于至少一些没有任何中间验证操作的脉冲。在一个脉冲之后，但是在将存储器偏置在下一个脉冲之前，不会中断，源和位线电平可以保持浮动。

45. 发明授权

US07978526B2 Low noise sense amplifier array and method for nonvolatile memory 有权
标题翻译：低噪声感知放大器阵列和非易失性存储器的方法
公开(公告)号：US07978526B2
公开(公告)日：2011-07-12
申请号：US12563918
申请日：2009-09-21
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee
IPC分类号： G11C16/26
CPC分类号： G11C7/02 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/5642 , G11C16/26
摘要： In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.
摘要翻译：在感测具有对应的一组感测模块的非易失性存储器单元的页面中，当识别出每个高电流单元时，它被锁定以进一步检测，而页面中的其他单元继续被感测。被锁定的感测模块处于锁定模式并变为非活动状态。当处于锁定模式时，来自感测模块的噪声源变得显着。通过将其位线耦合到邻近单元，噪声容易干扰相邻单元的感测。噪声也可以通过页面的公共源行耦合，以影响页面中单元格的持续感测的准确性。改进的感测模块和方法将噪声与锁定感测模块隔离，以影响在页面中感测存储器单元中仍然有效的其他感测模块。

46. 发明申请

US20110116320A1 VOLTAGE GENERATOR TO COMPENSATE SENSE AMPLIFIER TRIP POINT OVER TEMPERATURE IN NON-VOLATILE MEMORY 有权
标题翻译：电压发生器在非易失性存储器中补偿感测放大器触发点温度
公开(公告)号：US20110116320A1
公开(公告)日：2011-05-19
申请号：US12617860
申请日：2009-11-13
申请人： Fanglin Zhang , Jong Park , Man Mui , Alexander Chu , Seungpil Lee
发明人： Fanglin Zhang , Jong Park , Man Mui , Alexander Chu , Seungpil Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C11/5642
摘要： In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.
摘要翻译：在非易失性存储器系统中，电压发生器向用于感测电路的电压设置晶体管的栅极提供电压，以在感测节点处设置初始电压。在感测周期结束时，将感测节点的最终电压与作为电压感测晶体管的阈值电压的跳变点进行比较。为了解决温度变化和制造工艺变化，电压发生器包括与电压设定晶体管相匹配的晶体管和与电压感测晶体管匹配的晶体管。结果，即使初始电压和跳变点变化，初始电压和跳闸点之间的电压摆动也是恒定的。在特定实施方案中，电压发生器使用共源共栅电流镜电路，并从带隙电压电路接收参考电流。

47. 发明申请

US20100148856A1 Regulation of Recovery Rates in Charge Pumps 有权
标题翻译：调节收费泵的回收率
公开(公告)号：US20100148856A1
公开(公告)日：2010-06-17
申请号：US12337050
申请日：2008-12-17
申请人： Man Lung Lui , Seungpil Lee , Hao Thai Nguyen
发明人： Man Lung Lui , Seungpil Lee , Hao Thai Nguyen
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30
摘要： A method is presented of setting a frequency of a clock for a charge pump system including the clock and a charge pump. This includes setting an initial value for the frequency of the clock and, while operating the charge pump system using the clock running at the initial frequency value, determining the ramp rate of an output voltage for the charge pump during a recovery phase. The frequency of the clock is then adjusted so that the ramp rate of the output voltage for the charge pump during the recovery phase falls in a range not exceeding a predetermined maximum rate. A charge pump system is also described that includes a register having a settable value, where the charge pump clock frequency is responsive to the register value, and count and comparison circuitry is connectable to receive the pump's output voltage and the clock signal and determine from them the number of clock cycles the charge pump uses to recover from a reset value to a predetermined value.
摘要翻译：提出了一种设置包括时钟和电荷泵的电荷泵系统的时钟频率的方法。这包括设置时钟频率的初始值，并且在使用以初始频率值运行的时钟运行电荷泵系统的同时，在恢复阶段确定电荷泵的输出电压的斜坡率。然后调整时钟的频率，使得在恢复阶段期间电荷泵的输出电压的斜坡速率落在不超过预定最大速率的范围内。还描述了一种电荷泵系统，其包括具有可设置值的寄存器，其中电荷泵时钟频率响应寄存器值，并且计数和比较电路可连接以接收泵的输出电压和时钟信号并从它们确定电荷泵用于从复位值恢复到预定值的时钟周期数。

48. 发明授权

US07616506B2 Systems for complete word line look ahead with efficient data latch assignment in non-volatile memory read operations 有权
标题翻译：用于完整字线的系统在非易失性存储器读取操作中预测有效的数据锁存器分配
公开(公告)号：US07616506B2
公开(公告)日：2009-11-10
申请号：US11617550
申请日：2006-12-28
申请人： Man Lung Mui , Seungpil Lee
发明人： Man Lung Mui , Seungpil Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C16/3418
摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.
摘要翻译：由于基于相邻单元存储的电荷的电场耦合，可能会发生存储在非易失性存储单元中的诸如浮动栅极之类的电荷存储区域的视在电荷的变化。为了解释这种偏差，在阅读时应用补偿。当读取所选择的字线时，首先读取相邻的字线，并且将数据存储在每个位线的一组数据锁存器中。每个位线的一个锁存器存储数据来自相邻字线的指示。然后基于相邻字线上的单元格的不同状态，利用补偿来读取所选择的字线。每个感测模块使用来自相邻字线的数据来选择感测结果，并对其位线进行适当的补偿。来自相邻字线的数据在适当的时间用来自所选择的字线的数据被覆盖，并且指示被更新以反映锁存器存储来自所选字线的数据。数据锁存器的有效使用消除了分离锁存器来存储来自相邻字线的数据的需要。

49. 发明授权

US07606071B2 Compensating source voltage drop in non-volatile storage 有权
标题翻译：在非易失性存储器中补偿电源电压降
公开(公告)号：US07606071B2
公开(公告)日：2009-10-20
申请号：US11739501
申请日：2007-04-24
申请人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
发明人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3436
摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.
摘要翻译：解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。也可以使用这些方法的各种组合。在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。还可以补偿向前的身体偏差。

50. 发明授权

US07593265B2 Low noise sense amplifier array and method for nonvolatile memory 有权
标题翻译：低噪声感知放大器阵列和非易失性存储器的方法
公开(公告)号：US07593265B2
公开(公告)日：2009-09-22
申请号：US11966325
申请日：2007-12-28
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee
IPC分类号： G11C16/26
CPC分类号： G11C7/02 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/5642 , G11C16/26
摘要： In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.
摘要翻译：在感测具有对应的一组感测模块的非易失性存储器单元的页面中，当识别出每个高电流单元时，它被锁定以进一步检测，而页面中的其他单元继续被感测。被锁定的感测模块处于锁定模式并变为非活动状态。当处于锁定模式时，来自感测模块的噪声源变得显着。通过将其位线耦合到邻近单元，噪声容易干扰相邻单元的感测。噪声也可以通过页面的公共源行耦合，以影响页面中单元格的持续感测的准确性。改进的感测模块和方法将噪声与锁定感测模块隔离，以影响在页面中感测存储器单元中仍然有效的其他感测模块。

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