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1. 发明授权

US07532516B2 Non-volatile storage with current sensing of negative threshold voltages 有权
标题翻译：具有电流检测负阈值电压的非易失性存储器
公开(公告)号：US07532516B2
公开(公告)日：2009-05-12
申请号：US11771987
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：一种非易失性存储装置，其中对具有负阈值电压的非易失性存储元件执行电流检测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

2. 发明申请

US20080247238A1 METHOD FOR SENSING NEGATIVE THRESHOLD VOLTAGES IN NON-VOLATILE STORAGE USING CURRENT SENSING 有权
标题翻译：使用电流感测感知非挥发性储存中的负压阈值电压的方法
公开(公告)号：US20080247238A1
公开(公告)日：2008-10-09
申请号：US11771982
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/06 , G11C11/4091
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

3. 发明授权

US07606072B2 Non-volatile storage with compensation for source voltage drop 有权
标题翻译：非易失性存储器，用于补偿源电压降
公开(公告)号：US07606072B2
公开(公告)日：2009-10-20
申请号：US11739509
申请日：2007-04-24
申请人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
发明人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3436
摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.
摘要翻译：解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。也可以使用这些方法的各种组合。在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。还可以补偿向前的身体偏差。

4. 发明授权

US07606071B2 Compensating source voltage drop in non-volatile storage 有权
标题翻译：在非易失性存储器中补偿电源电压降
公开(公告)号：US07606071B2
公开(公告)日：2009-10-20
申请号：US11739501
申请日：2007-04-24
申请人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
发明人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3436
摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.
摘要翻译：解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。也可以使用这些方法的各种组合。在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。还可以补偿向前的身体偏差。

5. 发明授权

US07447079B2 Method for sensing negative threshold voltages in non-volatile storage using current sensing 有权
标题翻译：使用电流检测来检测非易失性存储器中的负阈值电压的方法
公开(公告)号：US07447079B2
公开(公告)日：2008-11-04
申请号：US11771982
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：在具有负阈值电压的所选择的非易失性存储元件的非易失性存储装置中执行电流感测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

6. 发明申请

US20080266963A1 COMPENSATING SOURCE VOLTAGE DROP IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中补偿电源电压
公开(公告)号：US20080266963A1
公开(公告)日：2008-10-30
申请号：US11739501
申请日：2007-04-24
申请人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
发明人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3436
摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.
摘要翻译：解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。也可以使用这些方法的各种组合。在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。还可以补偿向前的身体偏差。

7. 发明申请

US20080266964A1 NON-VOLATILE STORAGE WITH COMPENSATION FOR SOURCE VOLTAGE DROP 有权
标题翻译：具有补偿源电压下降的非易失性存储
公开(公告)号：US20080266964A1
公开(公告)日：2008-10-30
申请号：US11739509
申请日：2007-04-24
申请人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
发明人： Deepak Chandra Sekar , Nima Mokhlesi , Hao Thai Nguyen , Seungpil Lee , Man Lung Mui
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3436
摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.
摘要翻译：解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。也可以使用这些方法的各种组合。在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。还可以补偿向前的身体偏差。

8. 发明申请

US20080247228A1 NON-VOLATILE STORAGE WITH CURRENT SENSING OF NEGATIVE THRESHOLD VOLTAGES 有权
标题翻译：具有负电压电压的电流感测的非易失性存储
公开(公告)号：US20080247228A1
公开(公告)日：2008-10-09
申请号：US11771987
申请日：2007-06-29
申请人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Hao Thai Nguyen , Seungpil Lee , Man Lung Mui , Shahzad Khalid , Hock So , Prashanti Govindu , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C2211/5621 , G11C2211/5623 , G11C2211/5634 , G11C2211/565
摘要： A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.
摘要翻译：一种非易失性存储装置，其中对具有负阈值电压的非易失性存储元件执行电流检测。控制栅极读取电压被施加到非易失性存储元件的选定字线，并且源极和p阱电压分别施加到与非易失性存储元件相关联的源极和p阱。源极和p阱电压超过控制栅极读取电压，从而可以使用正极控制栅极读取电压。即使用于感测负阈值电压，也不需要负电荷泵来施加负字线电压。通过感测与在非易失性存储元件的NAND串中流动的固定电流相关联的电压降来确定非易失性存储元件的编程条件。

9. 发明授权

US08811075B2 Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: verify to program transition 有权
标题翻译：通过在NAND闪存的写操作期间均衡和调节源，阱和位线电平进行充电循环：验证程序转换
公开(公告)号：US08811075B2
公开(公告)日：2014-08-19
申请号：US13570779
申请日：2012-08-09
申请人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Jongmin Park , Man Lung Mui
发明人： Hao Thai Nguyen , Juan Carlos Lee , Seungpil Lee , Jongmin Park , Man Lung Mui
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
摘要翻译：在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。考虑脉冲和验证阶段之间的间隔。对于脉冲之后的间隔，但是在建立验证条件之前，可以将源极，位线以及可能的阱电平相等化，然后在期望的DC电平进行调节。在验证阶段之后，但是在将存储器应用于下一个脉冲之前，源和位线电平可以均衡为直流电平。

10. 发明授权

US08169831B2 High speed sense amplifier array and method for non-volatile memory 有权
标题翻译：高速读出放大器阵列和非易失性存储器的方法
公开(公告)号：US08169831B2
公开(公告)日：2012-05-01
申请号：US13100164
申请日：2011-05-03
申请人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
发明人： Hao Thai Nguyen , Man Lung Mui , Seungpil Lee , Fanglin Zhang , Chi-Ming Wang
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634
摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
摘要翻译：提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。预充电电路耦合到用于将节点充电到初始电压的节点。中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

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