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41. 发明授权

US06284593B1 Method for shallow trench isolated, contacted well, vertical MOSFET DRAM 失效
标题翻译：浅沟槽隔离方法，接触良好，垂直MOSFET DRAM
公开(公告)号：US06284593B1
公开(公告)日：2001-09-04
申请号：US09705652
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.
摘要翻译：提供了形成混合存储器单元的过程，该混合存储器单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

42. 发明授权

US06236077B1 Trench electrode with intermediate conductive barrier layer 失效
标题翻译：带中间导电阻挡层的沟槽电极
公开(公告)号：US06236077B1
公开(公告)日：2001-05-22
申请号：US09295136
申请日：1999-04-20
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10861 , H01L29/66181 , H01L29/945
摘要： Reduced scale trench capacitor structures of improved reliability and decreased series resistance are enabled by the creation and use of conductive barrier layers at intermediate points in the trench electrode structure. The conductive barrier layer is preferably either an intrinsically conductive compound barrier or a quantum conductive barrier. The capacitor structures are preferably characterized by a lower electrode region of very high dopant concentration.
摘要翻译：通过在沟槽电极结构的中间点处产生和使用导电阻挡层，可实现提高可靠性和降低串联电阻的缩小沟槽电容器结构。导电阻挡层优选为本征导电化合物屏障或量子导电屏障。电容器结构的特征在于具有非常高掺杂剂浓度的下电极区域。

43. 发明授权

US07790530B2 Dual port gain cell with side and top gated read transistor 失效
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07790530B2
公开(公告)日：2010-09-07
申请号：US12254960
申请日：2008-10-21
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

44. 发明授权

US07023041B2 Trench capacitor vertical structure 有权
标题翻译：沟槽电容器垂直结构
公开(公告)号：US07023041B2
公开(公告)日：2006-04-04
申请号：US10341187
申请日：2003-01-13
申请人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
发明人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/945 , H01L27/10861 , H01L27/10894 , H01L29/66181
摘要： A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.
摘要翻译：基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。

45. 发明授权

US06777733B2 Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays 有权
标题翻译：在EDRAM阵列中形成双功能高性能支持MOSFET的方法
公开(公告)号：US06777733B2
公开(公告)日：2004-08-17
申请号：US09862827
申请日：2001-05-22
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10894 , H01L27/10897
摘要： Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in forming the memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/EDRAM arrays having a gate conductor guard ring and/or local interconnections are also provided.
摘要翻译：提供双功能功能高性能支持金属氧化物半导体场效应晶体管（MOSFET）/嵌入式动态随机存取（EDRAM）阵列的方法。本文描述的方法减少了在形成存储器结构中使用的深UV掩模的数量，解耦支持和排列处理步骤，提供盐化栅极，源极/漏极区域和位线，并且在一些情况下提供局部互连，加工成本。还提供了双功能功能的高性能支持具有栅极导体保护环和/或局部互连的MOSFET / EDRAM阵列。

46. 发明授权

US06707095B1 Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation 有权
标题翻译：用于改进垂直MOSFET DRAM单元到单元隔离的结构和方法
公开(公告)号：US06707095B1
公开(公告)日：2004-03-16
申请号：US10290400
申请日：2002-11-06
申请人： Dureseti Chidambarrao , Jack A. Mandelman , Carl J. Radens
发明人： Dureseti Chidambarrao , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10867
摘要： A method is provided for forming a vertical transistor memory cell structure with back-to-back FET cells which are formed in a planar semiconductor substrate with a plurality of deep trenches having vertical FET devices and a plurality of capacitors each located in a separate trench that is formed in the semiconductor substrate. Bilateral outdiffusion strap regions are formed extending into a doped semiconductor well region in the substrate. There are confronting pairs of outdiffusion strap regions extending from adjacent deep benches into the doped well region. An isolation diffusion region is formed in the doped well separating the confronting isolation diffusion regions by extending therebetween.
摘要翻译：提供了一种用于形成具有背对背FET单元的垂直晶体管存储单元结构的方法，其形成在具有多个具有垂直FET器件的深沟槽的平面半导体衬底中，并且多个电容器分别位于单独的沟槽中，形成在半导体衬底中。形成延伸到衬底中的掺杂半导体阱区域中的双边扩散带区域。存在从相邻的深长板延伸到掺杂阱区域的面向对的向外扩散带区域。在掺杂阱中形成隔离扩散区，通过在相互隔离扩散区之间延伸来分离相对的隔离扩散区。

47. 发明授权

US06630379B2 Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch 失效
标题翻译：制造具有垂直MOSFET和3F位线间距的6F2沟槽电容器DRAM单元的方法
公开(公告)号：US06630379B2
公开(公告)日：2003-10-07
申请号：US10011556
申请日：2001-11-06
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.
摘要翻译：一种存储单元结构，包括平面半导体衬底。深沟槽位于半导体衬底中。深沟槽具有多个侧壁和底部。存储电容器位于深沟槽的底部。垂直晶体管向下延伸存储电容器上方的深沟槽的至少一个侧壁。晶体管具有在邻近深沟槽的衬底的平面中延伸的源极扩散。隔离层向下延伸与垂直晶体管相对的深沟槽的至少另一侧壁。浅沟槽隔离区沿垂直晶体管延伸的横向于侧壁的方向沿着衬底的表面延伸。栅极导体在深沟槽内延伸。一条字线延伸穿过深沟槽并连接到栅极导体。位线延伸在衬底的表面平面之上，并且具有与浅沟槽隔离区之间的源极扩散的接触。

48. 发明授权

US06573137B1 Single sided buried strap 有权
标题翻译：单面埋地带
公开(公告)号：US06573137B1
公开(公告)日：2003-06-03
申请号：US09603442
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。屏蔽材料沉积在存储电容器的节点导体上方。一层硅沉积在阻挡材料上。掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

49. 发明授权

US06441422B1 Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well 失效
标题翻译：具有接触P阱的超可扩展混合DRAM单元的结构和方法
公开(公告)号：US06441422B1
公开(公告)日：2002-08-27
申请号：US09706482
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Jai-hoon Sim
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Jai-hoon Sim
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867
摘要： An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.
摘要翻译：提供具有低结漏电的超可扩展混合存储器单元及其制造工艺。超可扩展混合存储器单元包含与身体区域的导电连接，从而避免由于掩埋带外扩散区域而导致的P阱的隔离。超可扩展混合存储器单元通过使用允许P阱保持连接到存储器单元的主体的比普通隔离区更浅的方式来避免上述情况。

50. 发明授权

US06440793B1 Vertical MOSFET 失效
公开(公告)号：US06440793B1
公开(公告)日：2002-08-27
申请号：US09757514
申请日：2001-01-10
申请人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
发明人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
IPC分类号： H01L218242
CPC分类号： H01L27/10841 , H01L21/2255 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

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