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41. 发明授权

US07611948B2 Methods of forming non-volatile memory device 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US07611948B2
公开(公告)日：2009-11-03
申请号：US11945477
申请日：2007-11-27
申请人： Jae-Hwang Sim , Yong-Sik Yim , Ki-Nam Kim , Jae-Kwan Park
发明人： Jae-Hwang Sim , Yong-Sik Yim , Ki-Nam Kim , Jae-Kwan Park
IPC分类号： H01L21/8247 , H01L21/8222
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S438/954
摘要： A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.
摘要翻译：形成非易失性存储器件的方法包括形成第一掩模图案，它们之间的距离可以相对较大。形成保形地覆盖第一掩模图案的距离调节层。在第一掩模图案之间的距离调节层的凹槽中形成第二掩模图案。

42. 发明申请

US20090206387A1 Non-volatile memory device, method of fabricating the same, and non-volatile semiconductor integrated circuit device, including the same 有权
标题翻译：非易失性存储器件及其制造方法以及包括该非易失性存储器件的非易失性半导体集成电路器件
公开(公告)号：US20090206387A1
公开(公告)日：2009-08-20
申请号：US12070422
申请日：2008-02-19
申请人： Chang-Seok Kang , Ki-Nam Kim
发明人： Chang-Seok Kang , Ki-Nam Kim
IPC分类号： H01L29/792 , H01L21/336 , H01L21/28
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/4234 , H01L29/792
摘要： A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and the wordline includes an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed.
摘要翻译：非易失性存储器件具有改进的操作特性。非易失性存储器件包括有源区; 在有源区域上形成的跨越有源区域的字线; 以及插入在有源区域和字线之间的电荷俘获层，其中有源区域和字线的交叉区域包括其中设置电荷捕获层的重叠区域和电荷捕获层是非重叠区域没有处理

43. 发明申请

US20070268749A1 Method for operating non-volatile memory device 审中-公开
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20070268749A1
公开(公告)日：2007-11-22
申请号：US11802282
申请日：2007-05-22
申请人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
发明人： Dae-Mann Kim , Wook-Hyun Kwon , Ki-Nam Kim , Chan-Kwang Park , Sang-Pil Sim
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0483 , G11C16/3409 , G11C16/345
摘要： A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.
摘要翻译：公开了一种操作非易失性存储器件的方法。存储单元包括分离源极区和漏极区的沟道区，隧道绝缘层，电荷存储层和形成在沟道区上的栅电极。该方法包括向栅电极施加负电压并向源区和漏区中的至少一个施加正电压，以将空穴注入到隧道绝缘层中，从而去除俘获在隧道绝缘层中的电子。

44. 发明申请

US20060124988A1 Methods of fabricating flash memory devices having self-aligned floating gate electrodes and related devices 审中-公开
标题翻译：制造具有自对准浮栅的闪存器件和相关器件的方法
公开(公告)号：US20060124988A1
公开(公告)日：2006-06-15
申请号：US11291142
申请日：2005-11-30
申请人： Sung-Hoi Hur , Jung-Dal Choi , Kyeong-Tae Kim , Jong-Ho Park , Jae-Duk Lee , Ki-Nam Kim
发明人： Sung-Hoi Hur , Jung-Dal Choi , Kyeong-Tae Kim , Jong-Ho Park , Jae-Duk Lee , Ki-Nam Kim
IPC分类号： H01L21/82 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating gate electrode is formed to extend beyond edges of the surface of the active region onto the isolation layer. A surface of the floating gate electrode adjacent the active region defines a plane, and the isolation layer is confined between the plane and the substrate. A control gate electrode is formed on a surface of the floating gate electrode opposite the active region. The control gate electrode may be formed to extend along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region. Related devices are also discussed.
摘要翻译：半导体存储器件通过形成从半导体衬底突出的有源区域形成，在邻近有源区域的相对侧壁的衬底上形成隔离层，以及在其相对侧壁之间的有源区域的表面上形成浮栅电极。浮栅电极被形成为延伸超过有源区表面的边缘到隔离层上。邻近有源区的浮栅电极的表面限定了一个平面，隔离层被限制在平面和衬底之间。控制栅电极形成在浮动栅电极的与有源区相对的表面上。控制栅电极可以被形成为沿着浮置栅电极的侧壁朝着衬底延伸超过由邻近有源区的浮栅的表面限定的平面。还讨论了相关设备。

45. 发明授权

US06909134B2 Ferroelectric memory device using via etch-stop layer and method for manufacturing the same 失效
标题翻译：使用通过蚀刻停止层的铁电存储器件及其制造方法
公开(公告)号：US06909134B2
公开(公告)日：2005-06-21
申请号：US10721689
申请日：2003-11-24
申请人： Yoon-Jong Song , Ki-Nam Kim , Sang-Woo Lee
发明人： Yoon-Jong Song , Ki-Nam Kim , Sang-Woo Lee
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/115 , H01L27/108
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.
摘要翻译：铁电存储器件及其制造方法。铁电存储器件包括形成在半导体衬底上的下层间绝缘层。铁电存储器件还包括设置在下层间绝缘层上的至少两个相邻的铁电电容器，形成在强电介质电容器上的层间绝缘层，留下暴露的铁电电容器的顶表面，形成在其上的图案化通孔蚀刻停止层层间绝缘层，使电容器的顶表面暴露，形成在图案化通孔蚀刻停止层上的上层间绝缘层，以及通常连接到至少两个相邻铁电电容器的板线。因此，可以显着增加铁电存储器件的集成。

46. 发明申请

US20050006680A1 Ferroelectric memory devices with improved ferroelectric properties and associated methods for fabricating such memory devices 失效
标题翻译：具有改进的铁电性能的铁电存储器件和用于制造这种存储器件的相关方法
公开(公告)号：US20050006680A1
公开(公告)日：2005-01-13
申请号：US10775016
申请日：2004-02-10
申请人： Yoon-Jong Song , Nak-Won Jang , Ki-Nam Kim
发明人： Yoon-Jong Song , Nak-Won Jang , Ki-Nam Kim
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.
摘要翻译：根据本发明的实施例，提供了包括设置在半导体衬底中的有源区上的晶体管和具有底电极，电容器 - 铁电层和顶电极的电容器的铁电存储器件。这些装置还可以包括与底部电极的侧表面相邻的至少一个平坦化层，使得平坦化层的顶表面和底部电极的顶表面形成平坦的表面。电容器 - 铁电体可以形成在该平坦表面上。器件还可以包括将底部电极电连接到晶体管的源极 - 漏极区域的插头。根据本发明实施例的铁电存储器件可以减小电容器的铁电性能降低。

47. 发明授权

US06787906B1 Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region 有权
标题翻译：位线焊盘和位线触头上的无边界触点，其形成在破坏区域中的局部蚀刻停止层
公开(公告)号：US06787906B1
公开(公告)日：2004-09-07
申请号：US09699589
申请日：2000-10-30
申请人： Won-Suk Yang , Sang-Ho Song , Hong-Sik Jeong , Ki-Nam Kim
发明人： Won-Suk Yang , Sang-Ho Song , Hong-Sik Jeong , Ki-Nam Kim
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/76804 , H01L21/76831 , H01L21/76832 , H01L27/10814 , H01L27/10885 , H01L27/10894
摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.
摘要翻译：选择性地在多层电路的层之间选择性地提供蚀刻停止层，以便允许随后的制造过程中的杂质脱气。蚀刻停止层形成在下面的螺柱上，以便在形成在上层中的上覆螺柱的形成期间用作对准目标。以这种方式，可以以相对致密的配置制造多层电路，例如存储器件。

48. 发明授权

US06768148B1 Devices with active areas having increased ion concentrations adjacent to isolation structures 失效
标题翻译：具有活性区域的器件具有与隔离结构相邻的离子浓度增加
公开(公告)号：US06768148B1
公开(公告)日：2004-07-27
申请号：US10403480
申请日：2003-03-31
申请人： Chang-Hyun Cho , Ki-Nam Kim , Sang-Hyeon Lee
发明人： Chang-Hyun Cho , Ki-Nam Kim , Sang-Hyeon Lee
IPC分类号： H01L2976
CPC分类号： H01L21/76237 , H01L21/823481
摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.
摘要翻译：可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域活动区域。将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度的第一活性区域中的离子，其大于第一和第二浓度。结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时晶体管。因此，可以抑制晶体管的阈值电压的降低。还公开了集成电路晶体管。

49. 发明授权

US06727542B2 Semiconductor memory device and method for manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06727542B2
公开(公告)日：2004-04-27
申请号：US10246392
申请日：2002-09-19
申请人： Ki-Nam Kim , Byung-Jun Park
发明人： Ki-Nam Kim , Byung-Jun Park
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L21/76897 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L28/55 , H01L28/91
摘要： A semiconductor memory device and a method for manufacturing the same are provided. The semiconductor memory device includes an oxide layer for isolating individual devices which define device areas so that a cell area and a peripheral circuit area are separated from each other on a semiconductor substrate, a plurality of MOS transistors, which are comprised of source areas, drain areas, and gates that are formed in the cell area and the peripheral circuit area, a bit line, which is formed on the plurality of MOS transistors and is electrically connected to the MOS transistor, a stack-shaped capacitor, which is comprised of a first electrode, a dielectric layer, and a second electrode between which the MOS transistors and the bit line in the cell area is interposed, a guard-ring pattern, which are interposed between the cell area and the peripheral circuit area, surrounds the cell area and is apart from the peripheral circuit area, and a contact fill for plate electrode, which is formed in the guard-ring pattern and is in contact with the second electrode that is formed on the internal sidewall and the bottom of the guard-ring pattern. The guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area, and thereby step caused by manufacture of the stack-shaped capacitor are removed during a manufacturing process, and the contact fill for plate electrode is formed in the guard-ring pattern, and thereby the ground resistance of the capacitor is reduced, and the electrical characteristics of the memory device are improved.
摘要翻译：提供半导体存储器件及其制造方法。半导体存储器件包括用于隔离各个器件的氧化物层，其限定器件区域，使得在半导体衬底上的单元区域和外围电路区域彼此分离，由源极区域构成的多个MOS晶体管，漏极形成在单元区域和外围电路区域中的区域和栅极，形成在多个MOS晶体管上并与MOS晶体管电连接的位线，堆叠形状的电容器，其由第一电极，电介质层和第二电极，MOS晶体管和单元区域中的位线之间插入有保护环图形，其间插入在单元区域和外围电路区域之间，围绕单元区域并且与外围电路区域分离，并且用于平板电极的接触填充物，其形成为保护环图案并与形成的第二电极接触在内侧壁和保护环图案的底部。保护环图案形成在单元区域和外围电路区域之间的边界周围，同时围绕单元区域，并且由此在制造过程中除去堆叠形电容器的制造所引起的步骤，并且板的接触填充电极形成为保护环图案，从而降低了电容器的接地电阻，并提高了存储器件的电气特性。

50. 发明授权

US06613621B2 Methods of forming self-aligned contact pads using a damascene gate process 有权
标题翻译：使用镶嵌门工艺形成自对准接触垫的方法
公开(公告)号：US06613621B2
公开(公告)日：2003-09-02
申请号：US09803244
申请日：2001-03-09
申请人： Hyung-Soo Uh , Kyu-Hynn Lee , Tae-Young Chung , Ki-Nam Kim , Yoo-Sang Hwang
发明人： Hyung-Soo Uh , Kyu-Hynn Lee , Tae-Young Chung , Ki-Nam Kim , Yoo-Sang Hwang
IPC分类号： H01L21338
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823437 , H01L21/823456 , H01L29/41783 , H01L29/66537 , H01L29/66545
摘要： Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.
摘要翻译：集成电路中的自对准触点可以形成在具有有源区的集成电路基板上。可以在绝缘层中形成沟槽，并且可以在沟槽中形成导电材料到凹陷在凹槽中的水平。绝缘材料可以形成在导电材料上的相对于绝缘层具有蚀刻选择性的凹槽中。然后可以形成与活性区域自对准的接触。

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