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41. 发明授权

US06556269B1 Connection assembly for reflective liquid crystal display and method 有权
标题翻译：反射液晶显示及连接方法
公开(公告)号：US06556269B1
公开(公告)日：2003-04-29
申请号：US10094310
申请日：2002-03-07
申请人： Hem P. Takiar , Ranjan J. Mathew
发明人： Hem P. Takiar , Ranjan J. Mathew
IPC分类号： G02F11345
CPC分类号： G02F1/13452 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H04N9/3105 , H04N9/317 , H05K1/118 , H05K3/361 , H01L2924/00014 , H01L2924/00
摘要： A connection assembly (40) for operably coupling a plurality of independent imaging devices (41, 41;, 41″) to an optical subsystem (42). The connection assembly (40) includes a unitary flex circuit device (43) having an elongated arm portion (45), and a plurality independent finger portions (46, 46′, 46″) extending from a distal end of the arm portion (45). Each finger portion (46, 46′, 46″) defines a coupling region (47, 47′, 47″) adapted to operably couple a respective imaging device (41, 41′, 41″) to a respective finger portion (46, 46′, 46″) for support thereof. The finger portions (46, 46′, 46″) are further adapted to strategically couple each respective imaging device (41, 41′, 41″) to the optical subsystem (42) as a unit. The flex circuit device (30) includes a plurality of circuits (65) terminating at respective terminals (40) of a coupling region (47) thereof. The terminals (66) supportively and communicably coupled to the bond pads (67) of the die (58) for support thereof. The coupling region (47) further includes an adhesive mount (76) mounting the flex circuit device (43) to the transparent plate to supportably suspend the display assembly (57) between the die (58) and the transparent plate (61).
摘要翻译：一种用于将多个独立成像装置（41,41,41“）可操作地耦合到光学子系统（42）的连接组件（40）。连接组件（40）包括具有细长臂部分（45）的单一柔性电路装置（43）和从臂部分的远端延伸的多个独立的指状部分（46,46'，46“） 45）。每个指部分（46,46'，46“）限定适于将相应的成像装置（41,41'，41”）可操作地耦合到相应的手指部分的耦合区域（47,47'，47“）（46,46'，46“），用于支撑它。手指部分（46,46'，46“）还适于将每个相应的成像装置（41,41'，41”）策略性地耦合到作为一个单元的光学子系统（42）。柔性电路装置（30）包括终止于其耦合区域（47）的各个端子（40）处的多个电路（65）。端子（66）支撑并可通信地耦合到模具（58）的接合焊盘（67）以用于其支撑。耦合区域（47）还包括将柔性电路装置（43）安装到透明板上以将显示组件（57）可支撑地悬挂在模具（58）和透明板（61）之间的粘合剂安装件（76）。

42. 发明授权

US06398034B1 Universal tape for integrated circuits 有权
标题翻译：集成电路通用磁带
公开(公告)号：US06398034B1
公开(公告)日：2002-06-04
申请号：US09515588
申请日：2000-02-29
申请人： Hem P. Takiar , Nikhil Vishwanath Kelkar
发明人： Hem P. Takiar , Nikhil Vishwanath Kelkar
IPC分类号： B65D8500
CPC分类号： B65D73/02 , H05K13/0084
摘要： The present invention provides a low cost carrier tape designed to store chips during transportation. The invention comprises a carrier tape which contains receptacle holes designed to secure chips onto the carrier tape by clasping onto the chip's electrical contacts. The receptacle holes prevent the chip from rotating and physically moving. The receptacle holes are formed in patterns to match the standardized electrical contact patterns of flip chip families. The diameters of the receptacle holes may be sized slightly smaller than the diameter of electrical contacts such that a chip is secured by “snap-fitting” each electrical contact into a receptacle hole. Relief slits may be formed on the edges of the receptacle holes to facilitate the “snap-fitting” of electrical contacts into receptacle holes.
摘要翻译：本发明提供了一种设计用于在运输期间存储芯片的低成本载带。本发明包括载带，该载带包含设计成通过扣紧芯片的电触点将芯片固定到载带上的插座孔。插座孔防止芯片旋转和物理移动。插座孔以图案形成以匹配倒装芯片族的标准化电接触图案。容纳孔的直径的尺寸可以略小于电触头的直径，使得芯片通过将每个电触头“卡扣配合”到插座孔中来固定。可以在容纳孔的边缘上形成浮雕狭缝，以便于将电触点“卡扣配合”到插孔中。

43. 发明授权

US06255141B1 Method of packaging fuses 有权
标题翻译：包装保险丝的方法
公开(公告)号：US06255141B1
公开(公告)日：2001-07-03
申请号：US09391137
申请日：1999-09-07
申请人： Inderjit Singh , Hem P. Takiar , Ranjan J. Mathew , Nikhil V. Kelkar
发明人： Inderjit Singh , Hem P. Takiar , Ranjan J. Mathew , Nikhil V. Kelkar
IPC分类号： H01L2182
CPC分类号： H01L23/62 , H01L2224/13
摘要： Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.
摘要翻译：描述了与集成电路器件一起封装外部保险丝的改进方法。提供了一对框带，每个框带具有一组相关的接触垫。将电阻浆料施加到接触垫组中的一个，并且通过固化位于接触垫组之间的电阻浆料将框带层压在一起。骰子安装到第二接触焊盘的相对侧，以形成具有整体封装的外部熔断器的集成电路器件。封装的装置最终被单独使用。在一些实施例中，接触垫每个都具有在每个管芯的相对侧上形成翅膀的下降的突片。当芯片是倒装芯片时，可以通过将裸片上的凸起和凸片翼尖焊接到基板来将装置附接到基板。在优选实施例中，电阻膏是正温度系数电阻膏。

44. 发明授权

US06177288B1 Method of making integrated circuit packages 有权
标题翻译：集成电路封装的方法
公开(公告)号：US06177288B1
公开(公告)日：2001-01-23
申请号：US09309723
申请日：1999-05-11
申请人： Hem P. Takiar
发明人： Hem P. Takiar
IPC分类号： H01L2166
CPC分类号： H01L22/32 , G01R31/2831 , H01L22/20 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： A method of producing and electrically testing a chip scale integrated circuit package includes the step of providing a panel having a plurality of chip scale packages assembled on the panel. Each of the chip scale packages are electrically isolated from one another by cutting any electrically conductive paths which electrically interconnect the chip scale packages to one another on the panel. The step of electrically isolating the chip scale packages is done without singulating the chip scale packages. The chip scale packages are then individually electrically tested while they remain physically connected to one another on the panel. After the chip scale packages are individually tested, the chip scale packages are singulated.
摘要翻译：制造和电测试芯片级集成电路封装的方法包括提供具有组装在面板上的多个芯片级封装的面板的步骤。每个芯片级封装通过切割将芯片尺寸封装彼此电连接在面板上的任何导电路径彼此电隔离。在不分离芯片级封装的情况下完成电隔离芯片级封装的步骤。芯片级封装然后被单独电测试，同时它们在面板上彼此物理连接。在对芯片级封装进行单独测试之后，将芯片级封装分开。

45. 发明授权

US5901043A Device and method for reducing thermal cycling in a semiconductor package 失效
标题翻译：用于减少半导体封装中的热循环的装置和方法
公开(公告)号：US5901043A
公开(公告)日：1999-05-04
申请号：US285344
申请日：1994-08-03
申请人： Peng-Cheng Lin , Hem P. Takiar
发明人： Peng-Cheng Lin , Hem P. Takiar
IPC分类号： H01L23/29 , H01L23/00 , H01L23/12 , H01L23/16 , H01L23/31 , H01L23/34 , H01L23/373 , H01L23/433 , H01L23/495 , H05K7/20
CPC分类号： H01L24/32 , H01L23/16 , H01L23/3738 , H01L23/4334 , H01L23/49503 , H01L23/564 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73215 , H01L2224/73265 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/3511
摘要： In semiconductor packaging, a method and device for reducing thermal stress on a die and for reinforcing the strength of a die. A thermally-conductive member is positioned in a cooperating manner with the die during the packaging process.
摘要翻译：在半导体封装中，用于降低模具上的热应力并增强模具的强度的方法和装置。在包装过程中，导热构件以与模具协同的方式定位。

46. 发明授权

US5783866A Low cost ball grid array device and method of manufacture thereof 失效
公开(公告)号：US5783866A
公开(公告)日：1998-07-21
申请号：US649395
申请日：1996-05-17
申请人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew , Hee Jhin Kim
发明人： Shaw Wei Lee , Hem P. Takiar , Ranjan J. Mathew , Hee Jhin Kim
IPC分类号： H01L21/48 , H01L21/60 , H01L21/673 , H01L21/68 , H01L23/13 , H01L23/498 , H01L23/48 , H01L23/04 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/6835 , H01L23/13 , H01L24/32 , H01L24/86 , H01L2221/68313 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/181
摘要： A panel of, for example, bismaleimide triazine (BT) or ceramic (Al.sub.2 O.sub.3) is chosen in size to be substantially filled with and taken up by end-result ball grid array (BGA) devices. The end-result devices are positioned closely together and take up substantially the entire area of the initial panel. Structural weakening is provided at appropriate places in the panel to allow the devices to be readily singulated.

47. 发明授权

US5495398A Stacked multi-chip modules and method of manufacturing 失效
公开(公告)号：US5495398A
公开(公告)日：1996-02-27
申请号：US462812
申请日：1995-06-05
申请人： Hem P. Takiar , Peng-Cheng Lin
发明人： Hem P. Takiar , Peng-Cheng Lin
IPC分类号： H01L25/18 , H01L23/495 , H01L25/065 , H01L25/07 , H05K1/00
CPC分类号： H01L23/49575 , H01L23/49531 , H01L24/49 , H01L2224/05554 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/4826 , H01L2224/48471 , H01L2224/4911 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2225/06568 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , Y10T29/49121
摘要： A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.

48. 发明授权

US5325268A Interconnector for a multi-chip module or package 失效
标题翻译：多芯片模块或封装的互连器
公开(公告)号：US5325268A
公开(公告)日：1994-06-28
申请号：US10964
申请日：1993-01-28
申请人： Manoj F. Nachnani , Hem P. Takiar
发明人： Manoj F. Nachnani , Hem P. Takiar
IPC分类号： H01L23/538 , H05K7/10
CPC分类号： H01L23/5382 , H01L23/5386 , H01L2224/05554 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/14 , H01L2924/19041
摘要： Integrated circuits having electrical interconnection in a multi-chip module or package is provided. Connections involving topological cross overs are achieved in the absence of multi-layers of metalization or vias. A plurality of metal traces in a single metalization layer are provided. Wire bonding issued to connect pads from two or more chips to a common metalization trace. Because the wire bonds can be vertically spaced from substrate traces, crossover connections can be achieved without an unwanted contact between traces and pads. A similar scheme can be used to provide connection to substrate pads.
摘要翻译：提供了在多芯片模块或封装中具有电互连的集成电路。在没有多层金属化或通孔的情况下实现涉及拓扑交叉的连接。提供单个金属化层中的多个金属迹线。引线接合，将焊盘从两个或多个芯片连接到通用的金属化迹线。因为引线键可以与衬底迹线垂直间隔开，所以可以实现交叉连接，而不会在迹线和焊盘之间发生不必要的接触。可以使用类似的方案来提供与衬底焊盘的连接。

49. 发明授权

US4707418A Nickel plated copper tape 失效
标题翻译：镀镍铜带
公开(公告)号：US4707418A
公开(公告)日：1987-11-17
申请号：US748876
申请日：1985-06-26
申请人： Hem P. Takiar , Divyesh P. Shah , Robert E. Hilton
发明人： Hem P. Takiar , Divyesh P. Shah , Robert E. Hilton
IPC分类号： H01L21/60 , H01L21/00 , C23F1/00 , H01L21/92
CPC分类号： H01L21/67144 , H01L2924/0002 , Y10T29/49121 , Y10T428/1291
摘要： An improved copper bump tape for tape automated bonding inhibits electromigration of the copper after bonding to a semiconductor device. The improved tape is characterized by the plating of a migration resistant metal onto the inner ends of connector beams of the tape. The migration resistant metal is coated onto all surfaces of the connector bump, except for the surface which is to be bonded to the semiconductor device. In this way, the surfaces of the bump which remain exposed after connection to the semiconductor are inhibited from electromigration.
摘要翻译：用于胶带自动接合的改进的铜凸块带在粘合到半导体器件之后抑制铜的电迁移。改进的带的特征在于将耐迁移金属电镀到带的连接器梁的内端上。除了要结合到半导体器件的表面之外，将耐迁移金属涂覆到连接器凸块的所有表面上。以这种方式，在与半导体连接之后保持暴露的凸块的表面被禁止电迁移。

50. 发明授权

US4367265A Intergranular insulation type semiconductive ceramic and method of producing same 失效
标题翻译：晶间绝缘型半导体陶瓷及其制造方法
公开(公告)号：US4367265A
公开(公告)日：1983-01-04
申请号：US251593
申请日：1981-04-06
申请人： Chyang J. Yu , Hem P. Takiar
发明人： Chyang J. Yu , Hem P. Takiar
IPC分类号： C04B35/468 , C04B35/47 , H01G4/12 , B32B9/04 , C04B35/00
CPC分类号： C04B35/4682 , C04B35/47 , H01G4/1281
摘要： An intergranular insulation type semiconductive ceramic having a high effective dielectric constant includes an electrically insulating dielectric layer situated in the grain boundaries of an alkaline-earth metal titanate, zirconate, or combination thereof. The alkaline-earth metals are barium, strontium, and calcium. The dielectric layer is made of a mixture of bismuth oxide (Bi.sub.2 O.sub.3) and one or more metal oxides from nickel oxide (NiO), alumina (Al.sub.2 O.sub.3), and cuprous oxide (Cu.sub.2 O).
摘要翻译：具有高有效介电常数的晶间绝缘型半导体陶瓷包括位于碱土金属钛酸盐，锆酸盐或其组合的晶界中的电绝缘介电层。碱土金属是钡，锶和钙。电介质层由氧化铋（Bi 2 O 3）和一种或多种来自氧化镍（NiO），氧化铝（Al 2 O 3）和氧化亚铜（Cu 2 O）的金属氧化物的混合物制成。

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