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41. 发明授权

US06639272B2 Charge compensation semiconductor configuration 有权
公开(公告)号：US06639272B2
公开(公告)日：2003-10-28
申请号：US10113343
申请日：2002-04-01
申请人： Dirk Ahlers , Armin Willmeroth , Hans Weber
发明人： Dirk Ahlers , Armin Willmeroth , Hans Weber
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/66712
摘要： Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric field can be chosen to have approximately the same magnitude in all of the compensation regions.

42. 发明授权

US4888840A Method for mercerizing textile fabric webs and apparatus for carrying out the method 失效
标题翻译：用于丝光纤维织物网的方法和用于实施该方法的装置
公开(公告)号：US4888840A
公开(公告)日：1989-12-26
申请号：US323200
申请日：1989-03-13
申请人： Hans Weber
发明人： Hans Weber
IPC分类号： D06B7/08
CPC分类号： D06B7/08
摘要： After leaving the hot lye bath (2) the fabric web (1) is immediately cooled down in a cooling zone (C) and only then passed to a residence zone (5) in which the lye acts on the fabric. Stretcing of the fabric web is then effected in a widthwise stretching zone (E), wherein it is again heated, preferably by a feed of hot weak lye. That combination of method steps provides optimum mercerizing effects with careful removal of shrinkage of the fabric.
摘要翻译：离开热碱液浴（2）后，织物网（1）立即在冷却区（C）中冷却，然后仅通过其中碱液作用在织物上的停留区（5）。然后在横向拉伸区域（E）中进行织物网的拉伸，其中其再次被加热，优选地通过热的弱碱液进料。该方法步骤的组合通过仔细地去除织物的收缩而提供最佳的丝光效果。

43. 发明授权

US08803205B2 Transistor with controllable compensation regions 有权
标题翻译：具有可控补偿区域的晶体管
公开(公告)号：US08803205B2
公开(公告)日：2014-08-12
申请号：US13484490
申请日：2012-05-31
申请人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
发明人： Armin Willmeroth , Franz Hirler , Hans Weber , Michael Treu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L27/088 , H01L27/098 , H01L29/0634 , H01L29/407 , H01L29/41766 , H01L29/42356 , H01L29/7803 , H01L29/7831
摘要： A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.
摘要翻译：半导体器件包括栅极端子，至少一个控制端子以及第一和第二负载端子以及至少一个器件单元。所述至少一个器件单元包括具有负载路径和控制端子的MOSFET器件，所述控制端子耦合到所述栅极端子以及具有负载路径和控制端子的JFET器件，所述负载路径与所述负载路径串联连接的MOSFET器件在负载端子之间。所述至少一个器件单元还包括具有负载路径和控制端子的第一耦合晶体管，所述负载路径耦合在所述JFET器件的控制端子与所述源极端子和所述栅极端子之一之间，并且所述控制端子耦合到晶体管器件的至少一个控制端子。

44. 发明授权

US08749018B2 Integrated semiconductor device having an insulating structure and a manufacturing method 有权
标题翻译：具有绝缘结构的集成半导体器件和制造方法
公开(公告)号：US08749018B2
公开(公告)日：2014-06-10
申请号：US12819856
申请日：2010-06-21
申请人： Matthias Stecher , Hans Weber , Lincoln O'Riain , Birgit von Ehrenwall
发明人： Matthias Stecher , Hans Weber , Lincoln O'Riain , Birgit von Ehrenwall
IPC分类号： H01L21/70
CPC分类号： H01L27/1207 , H01L21/187 , H01L21/743 , H01L21/76283 , H01L27/0251 , H01L27/1203 , H01L29/04 , H01L29/0878 , H01L29/1087 , H01L29/66681 , H01L29/7816
摘要： An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.
摘要翻译：提供集成半导体器件。集成半导体器件具有第二导电类型的第一半导体区域，与第一半导体区域形成pn结的第一导电类型的第二半导体区域，布置在第二导电类型的第二导电类型的非单晶半导体层半导体区域，布置在非单晶半导体层上的第一导电类型的第一阱和至少一个第二阱以及使第一阱与至少一个第二阱和非单晶半导体层绝缘的绝缘结构。此外，提供了一种用于形成半导体器件的方法。

45. 发明授权

US08716788B2 Semiconductor device with self-charging field electrodes 有权
标题翻译：具有自带场电极的半导体器件
公开(公告)号：US08716788B2
公开(公告)日：2014-05-06
申请号：US13250013
申请日：2011-09-30
申请人： Hans Weber , Franz Hirler , Stefan Gamerith
发明人： Hans Weber , Franz Hirler , Stefan Gamerith
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L29/0653 , H01L29/407 , H01L29/7813 , H01L29/868
摘要： Disclosed is a semiconductor device including a drift region of a first doping type, a junction between the drift region and a device region, and at least one field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode and arranged between the field electrode and the drift region, and having an opening, at least one of a field stop region and a generation region.
摘要翻译：公开了一种半导体器件，其包括第一掺杂类型的漂移区域，漂移区域和器件区域之间的结以及漂移区域中的至少一个场电极结构。场电极结构包括场电极，与场电极相邻并且设置在场电极和漂移区之间的场电极电介质，并且具有开场，场停止区和发生区中的至少一个。

46. 发明授权

US08637940B2 Semiconductor device with self-charging field electrodes and compensation regions 有权
标题翻译：具有自充电场电极和补偿区的半导体器件
公开(公告)号：US08637940B2
公开(公告)日：2014-01-28
申请号：US13331843
申请日：2011-12-20
申请人： Hans Weber
发明人： Hans Weber
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/407 , H01L29/7802 , H01L29/7813 , H01L29/861
摘要： A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, a compensation region of a second doping type, and at least one field electrode structure arranged between the drift region and the compensation region. The at least one field electrode includes a field electrode and a field electrode dielectric adjoining the field electrode. The field electrode dielectric is arranged between the field electrode and the drift region and between the field electrode and the compensation. The field electrode dielectric includes a first opening through which the field electrode is coupled to drift region and a second opening through which the field electrode is coupled to the compensation region.
摘要翻译：半导体器件包括第一掺杂类型的漂移区域，漂移区域和器件区域之间的结，第二掺杂类型的补偿区域以及布置在漂移区域和补偿区域之间的至少一个场电极结构。所述至少一个场电极包括场电极和邻接所述场电极的场电极电介质。场电极介质布置在场电极和漂移区之间以及场电极和补偿之间。场电极电介质包括第一开口，场电极通过该第一开口耦合到漂移区，第二开口通过该场电极耦合到补偿区。

47. 发明申请

US20140008717A1 Charge Compensation Semiconductor Device 有权
标题翻译：充电补偿半导体器件
公开(公告)号：US20140008717A1
公开(公告)日：2014-01-09
申请号：US13541884
申请日：2012-07-05
申请人： Hans Weber , Franz Hirler
发明人： Hans Weber , Franz Hirler
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/66727 , H01L29/7816
摘要： A semiconductor device is provided. The semiconductor device includes a semiconductor body and a source metallization which is arranged on the semiconductor body. The semiconductor body includes in a cross-section a drift region of a first conductivity type, a first body region of a second conductivity type which adjoins the drift region, a first compensation region of the second conductivity type which adjoins the first body region, has a lower maximum doping concentration than the first body region and forms a first pn-junction with the drift region, and a first charge trap. The first charge trap adjoins the first compensation region and includes a field plate and an insulating region which adjoins the drift region and partly surrounds the field plate. The source metallization is arranged in resistive electric connection with the first body region. Further, a method for producing a semiconductor device is provided.
摘要翻译：提供半导体器件。半导体器件包括半导体本体和布置在半导体本体上的源极金属化。半导体本体包括第一导电类型的漂移区域，邻接漂移区域的第二导电类型的第一体区域，邻接第一体区域的第二导电类型的第一补偿区域具有比第一体区低的最大掺杂浓度，并与漂移区形成第一pn结，以及第一电荷阱。第一电荷陷波器与第一补偿区域相邻并且包括场板和与漂移区域相邻并部分地围绕场板的绝缘区域。源极金属化被布置成与第一体区电阻电连接。此外，提供了一种用于制造半导体器件的方法。

48. 发明申请

US20130075801A1 SELF-ADJUSTED CAPACITIVE STRUCTURE 审中-公开
标题翻译：自调整电容结构
公开(公告)号：US20130075801A1
公开(公告)日：2013-03-28
申请号：US13242842
申请日：2011-09-23
申请人： Hans Weber , Roman Knoefler , Kurt Sorschag
发明人： Hans Weber , Roman Knoefler , Kurt Sorschag
IPC分类号： H01L29/94 , H01L29/92 , H01L21/02
CPC分类号： H01L29/945 , H01L27/0733 , H01L29/4236 , H01L29/66181
摘要： A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the first dielectric layer, forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap, forming a second dielectric layer on sidewalls and the bottom of the at least one second trench, and forming a second electrode layer on the second dielectric layer.
摘要翻译：一种在半导体本体中制造电容结构的方法，包括在半导体本体的第一表面中形成第一沟槽，在第一沟槽的侧壁和底部上形成第一电介质层，在第一介电层上形成第一电极层通过去除所述第一介电层的至少一部分以在所述第一表面中形成第一间隙而形成至少一个第二沟槽，并且通过加宽所述第一间隙，在所述至少一个的侧壁和底部上形成第二电介质层并且在所述第二介电层上形成第二电极层。

49. 发明申请

US20130001674A1 SEMICONDUCTOR DEVICE WITH VOLTAGE COMPENSATION STRUCTURE 有权
标题翻译：具有电压补偿结构的半导体器件
公开(公告)号：US20130001674A1
公开(公告)日：2013-01-03
申请号：US13174319
申请日：2011-06-30
申请人： Hans-Joachim Schulze , Hans Weber
发明人： Hans-Joachim Schulze , Hans Weber
IPC分类号： H01L29/78 , H01L29/06 , H01L21/22
CPC分类号： H01L29/7827 , H01L29/0634 , H01L29/0653 , H01L29/1054 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/66712 , H01L29/73 , H01L29/7395 , H01L29/7802 , H01L29/808 , H01L29/872
摘要： A semiconductor device with a high voltage compensation component is manufactured by etching a trench into an epitaxial semiconductor material doped with n-type dopant atoms and p-type dopant atoms and disposing a first semiconductor or insulating material along one or more sidewalls of the trench. The first semiconductor or insulating material has a dopant diffusion constant which is at least 2× different for the n-type dopant atoms than the p-type dopant atoms. A second semiconductor material is disposed in the trench along the first semiconductor or insulating material. The second semiconductor material has a different dopant diffusion constant than the first semiconductor or insulating material. More n-type dopant atoms or p-type dopant atoms are diffused from the epitaxial semiconductor material through the first semiconductor or insulating material into the second semiconductor material than the other type of dopant atoms so that a lateral charge separation occurs between the second semiconductor material and the epitaxial semiconductor material.
摘要翻译：通过将沟槽蚀刻成掺杂有n型掺杂剂原子和p型掺杂剂原子的外延半导体材料并且沿沟槽的一个或多个侧壁设置第一半导体或绝缘材料来制造具有高电压补偿分量的半导体器件。第一半导体或绝缘材料具有与p型掺杂剂原子相比对于n型掺杂剂原子至少为2×不同的掺杂剂扩散常数。第二半导体材料沿着第一半导体或绝缘材料设置在沟槽中。第二半导体材料具有与第一半导体或绝缘材料不同的掺杂剂扩散常数。比其他类型的掺杂剂原子，更多的n型掺杂剂原子或p型掺杂剂原子从外延半导体材料通过第一半导体或绝缘材料扩散到第二半导体材料中，使得在第二半导体材料和外延半导体材料。

50. 发明授权

US08288230B2 Method for producing a gate electrode structure 有权
标题翻译：栅电极结构的制造方法
公开(公告)号：US08288230B2
公开(公告)日：2012-10-16
申请号：US12894141
申请日：2010-09-30
申请人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
发明人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7803
摘要： A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure.
摘要翻译：具有栅电极结构的晶体管通过提供具有第一表面的半导体本体和从第一表面沿半导体本体的垂直方向延伸的第一牺牲层来制造。通过在与第一表面相邻的部分中去除牺牲层来形成从第一表面延伸到半导体本体的第一沟槽。通过在第一沟槽中各向同性蚀刻半导体本体来形成第二沟槽。通过去除第二沟槽下方的第一牺牲层的至少一部分，在第二沟槽下方形成第三沟槽。形成介电层，其至少覆盖第三沟槽的侧壁并仅覆盖第二沟槽的侧壁。栅电极形成在第二沟槽中的电介质层上。第二沟槽中的栅电极和电介质层形成栅电极结构。

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