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    • 41. 发明授权
    • Systems and methods for equalizer optimization in a storage access retry
    • 存储访问重试中均衡器优化的系统和方法
    • US07948699B2
    • 2011-05-24
    • US12348236
    • 2009-01-02
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • G11B5/09
    • G11B20/10009G11B20/10046G11B20/10055G11B20/10481G11B20/18G11B2020/183G11B2220/2516
    • Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
    • 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。
    • 42. 发明申请
    • Systems and Methods for Equalizer Optimization in a Storage Access Retry
    • 存储访问重试中均衡器优化的系统和方法
    • US20100172046A1
    • 2010-07-08
    • US12348236
    • 2009-01-02
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • Jingfeng LiuHongwei SongRichard RauschmayerYuan Xing Lee
    • G11B20/10
    • G11B20/10009G11B20/10046G11B20/10055G11B20/10481G11B20/18G11B2020/183G11B2220/2516
    • Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
    • 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。
    • 49. 发明申请
    • Systems and Methods for Storage Channel Testing
    • 存储通道测试的系统和方法
    • US20100265608A1
    • 2010-10-21
    • US12425757
    • 2009-04-17
    • Yuan Xing LeeGeorge MathewShaohua YangHongwel SongWeijun TanHao Zhong
    • Yuan Xing LeeGeorge MathewShaohua YangHongwel SongWeijun TanHao Zhong
    • G11B27/36
    • G11B20/182G11B2220/2516
    • Various embodiments of the present invention provide systems and methods for validating elements of storage devices. A an example, various embodiments of the present invention provide semiconductor devices that include a write path circuit, a read path circuit and a validation circuit. The write path circuit is operable to receive a data input and to convert the data input into write data suitable for storage to a storage medium. The read path circuit is operable to receive read data and to convert the read data into a data output. The validation circuit is operable to: receive the write data, augment the write data with a first noise sequence to yield a first augmented data series; and augment a derivative of the first augmented data series with a second noise sequence to yield the read data.
    • 本发明的各种实施例提供用于验证存储设备的元件的系统和方法。 作为示例,本发明的各种实施例提供包括写入路径电路,读取路径电路和验证电路的半导体器件。 写入路径电路可操作用于接收数据输入并将数据输入转换成适合于存储的写数据到存储介质。 读路径电路可操作以接收读数据并将读数据转换为数据输出。 验证电路可操作用于:接收写数据,用第一噪声序列增加写数据以产生第一增强数据序列; 并且用第二噪声序列来增加第一增强数据序列的导数以产生读取的数据。