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41. 发明授权

US08228706B2 Magnetic shift register memory device 失效
标题翻译：磁移位寄存器存储器
公开(公告)号：US08228706B2
公开(公告)日：2012-07-24
申请号：US12168379
申请日：2008-07-07
申请人： John K. DeBrosse , William J. Gallagher , Yu Lu
发明人： John K. DeBrosse , William J. Gallagher , Yu Lu
IPC分类号： G11C19/00
CPC分类号： G11C11/161 , G11C11/14 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C19/0808 , Y10S977/933
摘要： In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.
摘要翻译：在一个实施例中，本发明是磁移位寄存器存储器件。存储单元的一个实施例包括包括多个磁畴的磁柱，耦合到磁柱的读取器，用于从磁畴读取数据，用于存储从磁畴读取的数据的临时存储器和耦合到磁柱，用于将临时存储器中的数据写入磁畴。

42. 发明授权

US07535783B2 Apparatus and method for implementing precise sensing of PCRAM devices 失效
标题翻译：实现PCRAM设备精确检测的装置和方法
公开(公告)号：US07535783B2
公开(公告)日：2009-05-19
申请号：US11865134
申请日：2007-10-01
申请人： John K. DeBrosse , Thomas M. Maffitt , Mark C. H. Lamorey
发明人： John K. DeBrosse , Thomas M. Maffitt , Mark C. H. Lamorey
IPC分类号： G11C7/02
CPC分类号： G11C29/02 , G11C7/062 , G11C7/067 , G11C13/0004 , G11C13/004 , G11C29/026 , G11C29/028 , G11C2013/0054
摘要： A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.
摘要翻译：精密读出放大器装置包括：电流源，被配置为通过参考支路引入可调参考电流; 配置为将参考电流镜像到数据支路的电流镜，所述数据支路选择性地耦合到可编程电阻存储元件; 耦合到所述数据支脚的有源钳位装置，并且被配置为在所述存储元件上钳位固定电压，由此建立其固定的电流吸收能力; 以及差分读出放大器，其具有耦合到所述数据支路的第一输入端和耦合到所述基准支路的第二输入端; 其中每当所述参考电流小于所述存储元件的固定电流吸收能力时，所述差分读出放大器的输出呈现第一逻辑状态，并且每当所述参考电流超过所述固定电流吸收能力时，所述差分读出放大器的输出呈现第二逻辑状态。

43. 发明授权

US07453740B2 Method and apparatus for initializing reference cells of a toggle switched MRAM device 失效
标题翻译：用于初始化切换切换MRAM设备的参考单元的方法和装置
公开(公告)号：US07453740B2
公开(公告)日：2008-11-18
申请号：US11624707
申请日：2007-01-19
申请人： John K. DeBrosse , Mark C. H. Lamorey
发明人： John K. DeBrosse , Mark C. H. Lamorey
IPC分类号： G11C7/06
CPC分类号： G11C7/14 , G11C11/16 , G11C2207/2254
摘要： A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, and storing the result of the first read operation; inverting the value of one of the pair of the data cells; performing a second read operation of the reference cell, and storing the result of the second read operation; inverting the value of the other of the pair of the data cells; performing a third read operation of the reference cell, and storing the result of the third read operation. A majority compare operation of the results of the first, second and third operations is performed, wherein the result of the majority compare operation is the initial state of the reference cell.
摘要翻译：确定制造的存储器阵列中的参考单元的初始状态的方法包括通过将通过参考单元的电流与通过一对数据单元的平均电流进行比较来执行参考单元的第一读取操作，并且存储第一次读取操作; 反转一对数据单元之一的值; 执行参考单元的第二读取操作，并存储第二读取操作的结果; 反转一对数据单元中的另一个的值; 执行参考单元的第三读取操作，并存储第三读取操作的结果。执行第一，第二和第三操作的结果的多数比较操作，其中多数比较操作的结果是参考单元的初始状态。

44. 发明申请

US20080243972A1 HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME 有权
标题翻译：高密度平面磁畴壁记忆装置及其形成方法
公开(公告)号：US20080243972A1
公开(公告)日：2008-10-02
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： G06F15/02
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译：具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

45. 发明授权

US07239537B2 Method and apparatus for current sense amplifier calibration in MRAM devices 有权
标题翻译：用于MRAM器件中电流检测放大器校准的方法和装置
公开(公告)号：US07239537B2
公开(公告)日：2007-07-03
申请号：US10905585
申请日：2005-01-12
申请人： John K. DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
发明人： John K. DeBrosse , Dietmar Gogl , Stefan Lammers , Hans Viehmann
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.
摘要翻译：校准磁性随机存取存储器（MRAM）电流检测放大器包括与第一负载装置并联的第一多个调整晶体管，第一负载装置与读出放大器的数据侧相关联。与第二负载装置并联地选择性地配置第二组微调晶体管，第二负载装置与感测放大器的参考侧相关联。单独激活第一和第二多个微调晶体管，以补偿相对于读出放大器的数据和参考侧的器件失配。

46. 发明授权

US07135255B2 Layout impact reduction with angled phase shapes 失效
标题翻译：具有角度相位形状的布局冲击减少
公开(公告)号：US07135255B2
公开(公告)日：2006-11-14
申请号：US10249317
申请日：2003-03-31
申请人： Scott J. Bukofsky , John K. DeBrosse , Marco Hug , Lars W. Liebmann , Daniel J. Nickel , Juergen Preuninger
发明人： Scott J. Bukofsky , John K. DeBrosse , Marco Hug , Lars W. Liebmann , Daniel J. Nickel , Juergen Preuninger
IPC分类号： G01F9/00
CPC分类号： G03F1/30
摘要： A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.
摘要翻译：减少关键特征而不改变布局尺寸的线端缩短的相移掩模形状增加了所需的相移规则。相位特征给出一个有角度的延伸，其包括光刻缩短值。这允许将临界形状设计得更接近参考层，然后它可以没有成角度的延伸特征。通过沿着非临界部分延长特征，显着减少了给定装置段之外的相位掩模延伸特征; 将特征参考点移动到设备层; 并且将相延伸特征沿着装置段的非关键部分平坦化为L形或T形。应用这些设计规则允许在当前条件下绘制栅极导体，并将相位形状置于内部，而不会将栅极导体尺寸延伸到下一个特征。

47. 发明授权

US06704230B1 Error detection and correction method and apparatus in a magnetoresistive random access memory 有权
标题翻译：磁阻随机存取存储器中的误差检测和校正方法及装置
公开(公告)号：US06704230B1
公开(公告)日：2004-03-09
申请号：US10250201
申请日：2003-06-12
申请人： John K. DeBrosse , Heinz Hoenigschmid , Rainer Leuschner , Gerhard Mueller
发明人： John K. DeBrosse , Heinz Hoenigschmid , Rainer Leuschner , Gerhard Mueller
IPC分类号： G11C2900
CPC分类号： G11C7/24 , G06F11/106 , G11C11/406
摘要： The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.
摘要翻译：本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。此后，读出数据位和ECC校验位，并检测和校正任何错误。然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位并将ECC校验位存储到存储区域。

48. 发明授权

US5963489A Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device 失效
标题翻译：用于可修复半导体存储器件中冗余字线替换的方法和装置
公开(公告)号：US5963489A
公开(公告)日：1999-10-05
申请号：US47086
申请日：1998-03-24
申请人： Toshiaki Kirihata , John K. DeBrosse , Yohji Watanabe , Hing Wong
发明人： Toshiaki Kirihata , John K. DeBrosse , Yohji Watanabe , Hing Wong
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/806 , G11C29/848
摘要： A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.
摘要翻译：一种用于修复半导体存储器件的方法和装置。提供行冗余替换布置以修复由第一多个冗余真字字线和第二多个冗余补码字线组成的存储器件，以同时替换相同的第一数量的第一正常字线和相同的第二数目的第正常补码字线。地址重排序方案优选地实现为字线选择器电路并由冗余控制逻辑和地址输入控制，允许冗余的真（补）字线在进行修复时替换正常的真（补）字线。冗余替换布置确保始终保持位图的一致性，而不管存储器件是以正常操作还是以冗余模式操作。这种方法引入了增加冗余替换的灵活性，而不影响列访问速度。

49. 发明授权

US5614431A Method of making buried strap trench cell yielding an extended transistor 失效
标题翻译：制造扩展晶体管的掩埋带沟槽电池的方法
公开(公告)号：US5614431A
公开(公告)日：1997-03-25
申请号：US575311
申请日：1995-12-20
申请人： John K. DeBrosse
发明人： John K. DeBrosse
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861 , Y10S257/907
摘要： A process sequence, cell structure, and cell layout for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The process sequence may allow elimination of deep trench collar or cap deposition, or reduction of word line to word line capacitance. The cell prepared by the method allows a two lithographic feature transfer device channel length in an eight square folded bit line DRAM cell. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The cell requires only one additional mask (GPC) and minimal additional processing. The process sequence starts with deep trench (DT) processing, followed by deposition of SiO.sub.2, planarization and pad strip. Then gate SiO.sub.2, polysilicon, and pad are deposited. The structure is etched using a shallow trench isolation mask and filled with SiO.sub.2. After planarization, a thin insulator is deposited and the structure is etched again with a Gate Poly Contact mask. A gate conductor is then deposited. After a final etch, wiring is added.
摘要翻译：用于八平方折叠位线动态随机存取存储器（DRAM）单元的处理顺序，单元结构和单元布局允许两个光刻特征的传输设备通道长度。处理顺序可以允许消除深沟槽环或帽沉积，或者将字线减小到字线电容。通过该方法制备的电池允许在八个方形折叠的位线DRAM单元中的两个光刻特征传输器件沟道长度。该方法使用没有间隔物限定特征的常规加工技术，并且使用常规结构。电池只需要一个额外的掩模（GPC）和最少的附加处理。工艺顺序从深沟（DT）处理开始，随后沉积SiO 2，平面化和焊盘条。然后沉积栅极SiO2，多晶硅和焊盘。使用浅沟槽隔离掩模蚀刻该结构并填充SiO 2。在平坦化之后，沉积薄的绝缘体，并且用Gate Poly接触掩模再次蚀刻该结构。然后沉积栅极导体。最终蚀刻后，加入接线。

50. 发明授权

US5602051A Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level 失效
标题翻译：在给定的堆叠级上制造具有电隔离和电连接区域的堆叠电气装置的方法
公开(公告)号：US5602051A
公开(公告)日：1997-02-11
申请号：US540387
申请日：1995-10-06
申请人： John E. Cronin , John K. DeBrosse , Hing Wong
发明人： John E. Cronin , John K. DeBrosse , Hing Wong
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L2924/0002
摘要： An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.
摘要翻译：公开了一种用于隔离彼此定位的电导体的改进方法。这些导体通常彼此接触，因为用于制造多个导电元件（例如非常致密的半导体结构）的图案化和蚀刻步骤有些不精确。该方法包括在下导体的上表面中形成凹部，然后用氧化物型材料至少部分地填充凹部。该方法在叠层电容器单元的构造中特别有价值。使用该技术制备的细胞也构成本发明的一部分。

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