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41. 发明申请

US20120161092A1 PHASE CHANGE MEMORY AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：相变记忆及其制作方法
公开(公告)号：US20120161092A1
公开(公告)日：2012-06-28
申请号：US13176632
申请日：2011-07-05
申请人： Fumitake Mieno , Youfeng He
发明人： Fumitake Mieno , Youfeng He
IPC分类号： H01L45/00 , H01L33/08
CPC分类号： H01L45/1213 , H01L27/15 , H01L27/24 , H01L45/06
摘要： The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.
摘要翻译：本发明提供一种相变存储器和形成相变存储器的方法。相变存储器包括存储区域和外围电路区域。外围电路区域具有周边基板，外围基板中的多个外围浅沟槽隔离（STI）单元，以及周边基板上的周边基板之间和周边STI单元之间的至少一个MOS晶体管。存储区域具有存储基板，存储基板上的N型离子掩埋层，N型离子掩埋层上的多个垂直LED，垂直LED之间的多个存储浅沟槽隔离（STI）单元，以及在垂直LED上和存储STI单元之间的多个相变层。存储STI单元的厚度基本上等于垂直LED的厚度。外围STI单元的厚度基本上等于存储STI单元的厚度。 N型导电区域包含SiC。 P型导电区域的顶部与外围基板的顶部齐平。含有SiC的N型导电区域通过垂直LED降低漏极电流并提高垂直LED的电流效率。外围电路区域可以正常工作，而不会对相变存储器的性能产生不利影响。

42. 发明授权

US08148272B2 Application of millisecond heating source for surface treatment 有权
标题翻译：应用毫秒加热源进行表面处理
公开(公告)号：US08148272B2
公开(公告)日：2012-04-03
申请号：US12842017
申请日：2010-07-22
申请人： David Gao , Fumitake Mieno
发明人： David Gao , Fumitake Mieno
IPC分类号： H01L21/311 , H01L21/316
CPC分类号： H01L21/268 , H01L21/02046 , H01L21/02057 , H01L21/02098 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848 , Y10S134/902
摘要： A method for fabricating semiconductor devices, e.g., strained silicon MOS device, includes providing a semiconductor substrate (e.g., silicon wafer) having a surface region, which has one or more contaminants and an overlying oxide layer. The one or more contaminants is at least a carbon species. The method also includes processing the surface region using at least a wet process to selectively remove the oxide layer and expose the surface region. The method further includes subjecting the surface region to a laser treatment process for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants provided on the surface region. The method also includes removing the laser treatment process to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.
摘要翻译：制造半导体器件（例如应变硅MOS器件）的方法包括提供具有表面区域的半导体衬底（例如，硅晶片），该表面区域具有一个或多个污染物和上覆氧化物层。一种或多种污染物是至少一种碳类。该方法还包括使用至少湿法处理表面区域以选择性地去除氧化物层并暴露表面区域。该方法还包括使表面区域进行激光处理过程，持续时间小于1秒，以将表面区域的温度升高至大于1000摄氏度，以去除表面区域上提供的一种或多种污染物。该方法还包括去除激光处理过程，以在小于1秒的时间段内将温度降低至约300至约600摄氏度。

43. 发明授权

US08101478B2 TFT MONOS or SONOS memory cell structures 有权
标题翻译： TFT MONOS或SONOS存储单元结构
公开(公告)号：US08101478B2
公开(公告)日：2012-01-24
申请号：US12259032
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/8239
CPC分类号： H01L29/792 , H01L27/1203 , H01L29/66833
摘要： A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an oxide-nitride-oxide (ONO) layer overlying the P− polysilicon layer; and at least one control gate overlying the ONO layer. In one embodiment, the control gate is made of a metal layer. In another embodiment, the control gate is made of a P+ polysilicon layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
摘要翻译：提供了具有薄膜晶体管（TFT）金属氧化物 - 氮化物 - 氧化物半导体（MONOS）或半导体 - 氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元结构的器件。该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。介电层与第一表面相关联。所述一个或多个源区或漏区中的每一个包括在导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。另外，该器件包括覆盖共面表面的P-多晶硅层，覆盖在P多晶硅层上的氧化物 - 氮化物 - 氧化物（ONO）层; 以及覆盖ONO层的至少一个控制门。在一个实施例中，控制栅极由金属层制成。在另一实施例中，控制栅极由P +多晶硅层制成。提供了制造相同存储单元结构的方法，并且可以重复三维地集成结构。

44. 发明申请

US20100001280A1 TFT MONOS OR SONOS MEMORY CELL STRUCTURES 有权
标题翻译： TFT MONOS或SONOS存储器单元结构
公开(公告)号：US20100001280A1
公开(公告)日：2010-01-07
申请号：US12259032
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/792 , H01L27/1203 , H01L29/66833
摘要： A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an oxide-nitride-oxide (ONO) layer overlying the P− polysilicon layer; and at least one control gate overlying the ONO layer. In one embodiment, the control gate is made of a metal layer. In another embodiment, the control gate is made of a P+ polysilicon layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
摘要翻译：提供了具有薄膜晶体管（TFT）金属氧化物 - 氮化物 - 氧化物半导体（MONOS）或半导体 - 氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元结构的器件。该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。介电层与第一表面相关联。所述一个或多个源区或漏区中的每一个包括在导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。另外，该器件包括覆盖共面表面的P-多晶硅层，覆盖在P多晶硅层上的氧化物 - 氮化物 - 氧化物（ONO）层; 以及覆盖ONO层的至少一个控制门。在一个实施例中，控制栅极由金属层制成。在另一实施例中，控制栅极由P +多晶硅层制成。提供了制造相同存储单元结构的方法，并且可以重复三维地集成结构。

45. 发明申请

US20100001271A1 SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON MAS MEMORY CELL STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有非晶硅MAS记忆体结构的半导体器件及其制造方法
公开(公告)号：US20100001271A1
公开(公告)日：2010-01-07
申请号：US12259015
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L45/00 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11568 , H01L27/12 , H01L29/8616
摘要： A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.
摘要翻译：具有非晶硅（a-Si）金属 - 氧化铝半导体（MAS）存储单元结构的半导体器件。该器件包括衬底，覆盖在衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域，其中n型a-Si的共面表面和电介质层。另外，器件包括p-i-n a-Si二极管结。该器件还包括在a-Si p-i-n二极管结上的氧化铝电荷俘获层和覆盖氧化铝层的金属控制栅极。提供了一种用于制造a-Si MAS存储单元结构并且可以重复三维地集成结构的方法。

46. 发明申请

US20100001270A1 AMORPHOUS SILICON MONOS OR MAS MEMORY CELL STRUCTURE WITH OTP FUNCTION 有权
标题翻译：具有OTP功能的非晶硅单体或MAS记忆体细胞结构
公开(公告)号：US20100001270A1
公开(公告)日：2010-01-07
申请号：US12258950
申请日：2008-10-27
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L29/02 , H01L21/84
CPC分类号： H01L27/11206 , H01L27/112
摘要： A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
摘要翻译：具有一次可编程（OTP）功能的具有非晶硅（a-Si）金属氧化物 - 氮化物 - 氧化物 - 硅（MONOS）或金属 - 氧化铝 - 硅（MAS）存储单元结构的半导体器件。该器件包括衬底，覆盖衬底的第一电介质层和嵌入在第一介电层中的一个或多个源极或漏极区域，其具有n型a-Si的共面表面和第一介电层。另外，器件包括p-i-n a-Si二极管结。该器件还包括在a-Si p-i-n二极管结上的第二介质层和覆盖第二介电层的金属控制栅极。可选地，具有OTP功能的器件包括在n型a-Si层和金属控制栅极之间形成的导电路径。提供了制造相同存储单元结构的方法，并且可以重复三维地集成结构。

47. 发明申请

US20080132008A1 METHOD FOR FABRICATING LANDING POLYSILICON CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES 有权
公开(公告)号：US20080132008A1
公开(公告)日：2008-06-05
申请号：US11609758
申请日：2006-12-12
申请人： Fumitake Mieno
发明人： Fumitake Mieno
IPC分类号： H01L21/8232
CPC分类号： H01L21/3141 , H01L21/02178 , H01L21/0228 , H01L21/02304 , H01L21/3162 , H01L21/7684 , H01L21/76895 , H01L21/76897 , H01L27/105 , H01L27/1052
摘要： A method for forming an integrated circuit device, e.g., memory, logic. The method includes providing a semiconductor substrate (e.g., silicon wafer) comprising a surface region and forming a polysilicon layer overlying the surface region. Preferably, the polysilicon layer is doped with an impurity to provide conductive characteristics. The method forms a cap layer (e.g., silicon nitride, silicon oxynitride) overlying the polysilicon layer. The method forms an Al2O3 layer using atomic layer deposition overlying the polysilicon layer to form a sandwich structure including the polysilicon layer, cap layer, and Al2O3 layer. The method includes patterning the sandwich layer to form a plurality of gate structures. Each of the gate structures includes a portion of the polysilicon layer, a portion of the cap layer, and a portion of the Al2O3 layer. The method forms an interlayer dielectric material (e.g., BPSG, FSG) having an upper surface overlying the plurality of gate structures. The method also includes patterning the interlayer dielectric material to form an opening in a portion of the interlayer dielectric material to expose each of the gate structures and filling the opening with a polysilicon fill material to a vicinity of the upper surface of the interlayer dielectric material. Preferably, the fill material is doped using an impurity. The method also performs a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer concurrently with a portion of the polysilicon fill material and maintains the chemical mechanical polishing process until a portion of the Al2O3 layer overlying one of the gate structures has been exposed. The method uses portions of the Al2O3 layer as a polish stop while preventing any exposure of any portion of the polysilicon layer.

48. 发明授权

US5264038A Chemical vapor deposition system 失效
标题翻译：化学气相沉积系统
公开(公告)号：US5264038A
公开(公告)日：1993-11-23
申请号：US567224
申请日：1990-08-14
申请人： Tatsushi Hara , Nobuhiro Misawa , Toshiya Suzuki , Takayuki Ohba , Fumitake Mieno , Akio Yamaguchi
发明人： Tatsushi Hara , Nobuhiro Misawa , Toshiya Suzuki , Takayuki Ohba , Fumitake Mieno , Akio Yamaguchi
IPC分类号： C23C16/44 , C23C16/04 , C23C16/448 , C23C16/455 , H01L21/205 , H01L21/28 , H01L21/285 , C23C16/46
CPC分类号： C23C16/45517 , C23C16/04 , C23C16/455 , C23C16/45591
摘要： A chemical vapor deposition (CVD) system for depositing a material selectively on a part of a substrate comprises a reaction chamber in which a CVD process is performed, a substrate holder and substrate heater provided within the reaction chamber, a gas inlet fixture provided on the reaction chamber for introducing one or more CVD source gases into the reaction chamber, and a reactant distribution fixture provided on the gas inlet fixture within the reaction chamber for controlling distribution of the reactant species in the reaction chamber, wherein the reactant distribution fixture defines a subspace surrounding the substrate within the space of the reaction chamber such that the subspace has a dimension, measured in a direction generally perpendicular to the surface of the substrate such that the dimension is at least less than one half of the mean free path of the reactant species realized inside the space of the reaction chamber during the CVD process and such that an opening is formed for communicating the subspace inside the reaction distribution means with the rest of the space of the reaction chamber for freely passing product species formed as a result of the chemical reaction at the surface of the substrate.

49. 发明授权

US5103285A Silicon carbide barrier between silicon substrate and metal layer 失效
标题翻译：硅衬底和金属层之间的硅碳化物屏障
公开(公告)号：US5103285A
公开(公告)日：1992-04-07
申请号：US286611
申请日：1988-12-19
申请人： Yuji Furumura , Fumitake Mieno , Takashi Eshita , Kikuo Itoh , Masahiko Doki
发明人： Yuji Furumura , Fumitake Mieno , Takashi Eshita , Kikuo Itoh , Masahiko Doki
IPC分类号： H01L21/205 , H01L29/45 , H01L29/78
CPC分类号： H01L29/456
摘要： A silicon carbide layer between a silicon substrate or layer and a metal layer because silicon carbide has many properties similar to those of silicon, has a very slow diffusion rate of a metal through the silicon carbide, or prevents a diffusion of a metal into the silicon, and can be deposited by CVD, which has an advantage of a good coverage over a step portion such as a contact window.

50. 发明授权

US4876219A Method of forming a heteroepitaxial semiconductor thin film using amorphous buffer layers 失效
标题翻译：使用非晶缓冲层形成异质外延半导体薄膜的方法
公开(公告)号：US4876219A
公开(公告)日：1989-10-24
申请号：US318638
申请日：1989-03-03
申请人： Takashi Eshita , Fumitake Mieno , Yuji Furumura , Takuya Watanabe
发明人： Takashi Eshita , Fumitake Mieno , Yuji Furumura , Takuya Watanabe
IPC分类号： H01L21/20 , H01L21/205
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02502 , H01L21/02507 , H01L21/02546 , H01L21/02658 , Y10S148/025 , Y10S148/072 , Y10S148/097 , Y10S148/154 , Y10S148/169 , Y10S438/933
摘要： A method of forming a semiconductor thin layer on a silicon substrate comprising the steps of depositing a first amorphous layer of a compound semiconductor (e.g., GaAs) on the silicon substrate, and growing a first epitaxial layer of the compound semiconductor on the amorphous layer, characterized in that the method comprises the steps of: after the epitaxial growth step, depositing a second amorphous layer of the compound semiconductor on the first epitaxial layer, and growing a second epitaxial layer of the compound semiconductor on the second amorphous layer. The obtained GaAs/Si substrate has a reduced dislocation density.

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