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41. 发明授权

US07212050B2 System and method for synthesizing a clock at digital wrapper (FEC) and base frequencies using one precision resonator 有权
标题翻译：使用一个精密谐振器在数字封装（FEC）和基频合成时钟的系统和方法
公开(公告)号：US07212050B2
公开(公告)日：2007-05-01
申请号：US11016314
申请日：2004-12-17
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03L7/06
CPC分类号： H03L7/099 , H03L7/0812 , H03L7/0891 , H03L7/183 , H03L7/23
摘要： A precision PLL based transceiver having a single precision SAW or crystal resonator is configured to lock onto multiple different input frequencies and output generated clocks at the multiple different frequencies. The input reference frequency may be higher or lower than the resonator frequency. A fraction of two whole numbers describing a ratio of the resonator frequency to a given input frequency reference is first obtained. One of the numerator or denominator in the fraction is used to set the divide value of a first frequency divider coupling a VFO based on the resonator to a feedback input on a PFD. The other of the numerator or denominator is used to set a second frequency divider coupling the input frequency reference signal to the PFD. A first frequency multiplier is given a multiplication factor matching the divide value of the second frequency divider, and used to couple the output of the first frequency divider to the output of the PLL. Alternatively, a second frequency divider may be inserted between the reference frequency input and the PFD to match the frequency, or a multiple thereof, of the VFO output, which may bypass the first frequency divider in the feedback path to the PFD.
摘要翻译：具有单精度SAW或晶体谐振器的精密PLL收发器配置成锁定在多个不同的输入频率上，并以多个不同的频率输出产生的时钟。输入参考频率可以高于或低于谐振器频率。首先获得描述谐振器频率与给定输入频率参考值的比率的两个整数的一部分。分数中的分子或分母之一用于将基于谐振器的VFO的第一分频器的分频值设置为PFD上的反馈输入。分子或分母中的另一个用于设置将输入频率参考信号耦合到PFD的第二分频器。第一倍频器被给予与第二分频器的分频匹配的乘法因子，并且用于将第一分频器的输出耦合到PLL的输出。或者，可以在参考频率输入和PFD之间插入第二分频器以匹配可以绕过PFD的反馈路径中的第一分频器的VFO输出的频率或其倍数。

42. 发明授权

US07187222B2 CMOS master/slave flip-flop with integrated multiplexor 失效
标题翻译：具有集成多路复用器的CMOS主/从触发器
公开(公告)号：US07187222B2
公开(公告)日：2007-03-06
申请号：US11016430
申请日：2004-12-17
申请人： David Meltzer , Muralikumar A. Padaparambil
发明人： David Meltzer , Muralikumar A. Padaparambil
IPC分类号： H03K3/289
CPC分类号： H03K3/356139
摘要： A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pull-up loads and current source typically required for a stand-alone multiplexor are eliminated. Subsequently, the size of the present hybrid master-slave latch is smaller and consumes less power than a traditional combination of an independent multiplexor and master-slave latch. Since the master latching circuitry feeds only into the slave latching circuitry, the pull-up loads and the current sources of the master latching circuitry and slave latching circuitry may be optimized separately for achieving faster performance or less power consumption.
摘要翻译： CML主从锁存器将逻辑并入其主锁存电路，以将多路复用功能并入到触发器中。复用逻辑利用主锁存电路的上拉负载和电流源。以这种方式，消除了独立复用器通常需要的上拉负载和电流源。随后，当前的混合主 - 从锁存器的大小比独立多路复用器和主 - 从锁存器的传统组合消耗更少的功率。由于主锁存电路仅馈入从锁存电路，因此可以单独优化主锁存电路和从锁存电路的上拉负载和电流源，以实现更快的性能或更低的功耗。

43. 发明授权

US07167058B2 Temperature compensation for a variable frequency oscillator without reducing pull range 失效
标题翻译：可变频率振荡器的温度补偿，不减小拉范围
公开(公告)号：US07167058B2
公开(公告)日：2007-01-23
申请号：US10733094
申请日：2003-12-11
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03B1/00
CPC分类号： H03L1/022 , H03B5/04 , H03L1/023 , H03L7/00 , Y10S331/03
摘要： A variable frequency oscillator having multiple, independent frequency control inputs, each coupled to a respective tuning sub-circuit. The tuning sub-circuits are connected in parallel with each other and with a resonator module, which may be a quartz crystal, inductor, or other reactance component. Each tuning sub-circuit consists of two varactors with their respective cathodes coupled to each other and to their corresponding frequency control input. By having the tuning sub-circuits connected in parallel to the resonator, the overall frequency pull range of each frequency control input remains unaffected by the activation of any other frequency control input. Preferably, at least one frequency control input is a temperature compensation control input that can maintain the variable oscillator insensitive to temperature variations while the remaining frequency control inputs provide functional frequency control.
摘要翻译：具有多个独立频率控制输入的可变频率振荡器，每个都耦合到相应的调谐子电路。调谐子电路彼此并联并且具有可以是石英晶体，电感器或其它电抗分量的谐振器模块。每个调谐子电路由两个变容二极管组成，它们各自的阴极相互耦合并连接到它们对应的频率控制输入端。通过使调谐子电路与谐振器并联连接，每个频率控制输入的总频率拉动范围不受任何其它频率控制输入的激活的影响。优选地，至少一个频率控制输入是温度补偿控制输入，其可以保持可变振荡器对温度变化不敏感，而剩余频率控制输入提供功能频率控制。

44. 发明授权

US07157942B2 Digital frequency difference detector with inherent low pass filtering and lock detection 有权
标题翻译：数字频差检测器，具有固有的低通滤波和锁定检测
公开(公告)号：US07157942B2
公开(公告)日：2007-01-02
申请号：US11007546
申请日：2004-12-08
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03D3/24 , H03D13/00
CPC分类号： H03L7/085 , H03D13/002 , H03L7/095
摘要： A structure and method for implementing a fully digital frequency difference detector uses an n-bit counter to count cycles of a reference clock signal and an m-bit counter to count cycles of a synthesized clock signal, where m is greater than n. The two counters operate concurrently, and both are halted when the n-bit counter overflows into its nth bit position. Two latches respectively record if bits n and (n+1) in the m-bit become set prior to the n-bit counter overflowing. By observing the state of the two latches and the state of a predefined bit range within the m-counter, the frequency difference detector can determined if the frequency of the synthesized clock is greater than, less than, or locked to the frequency of the reference clock signal.
摘要翻译：用于实现全数字频差检测器的结构和方法使用n位计数器对参考时钟信号和m位计数器的周期进行计数，以计数合成时钟信号的周期，其中m大于n。两个计数器同时运行，当n位计数器溢出到其第n个位位置时，两个计数器都停止。两个锁存器分别记录在n位计数器溢出之前m位中的位n和（n + 1）是否被置位。通过观察两个锁存器的状态和m个计数器内的预定义位范围的状态，频率差检测器可以确定合成时钟的频率是否大于，小于或锁定到参考的频率时钟信号。

45. 发明授权

US07082178B2 Lock detector circuit for dejitter phase lock loop (PLL) 失效
公开(公告)号：US07082178B2
公开(公告)日：2006-07-25
申请号：US10016915
申请日：2001-12-14
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03D3/24
CPC分类号： H03L7/0891 , H03L7/095 , Y10S331/02
摘要： A phase lock loop lock detect circuit determines whether an output signal of the phase lock loop is in phase-frequency synchronization with an input reference timing signal and provides an unlock alarm signal indicating that the output signal of a phase lock loop is no longer in phase-frequency synchronization with an input reference timing signal. The lock detection circuit has a first logic function circuit to combine a frequency increase signal and a frequency decrease signal of said phase lock loop to provide a frequency deviation signal. The first logic function in the preferred embodiment of this invention is an OR gate. The output of the first logic function circuit is an input to a second logic function circuit. The second logic function circuit combines the frequency deviation signal with the input reference signal, which is applied to a second input of the second logic function, to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said input reference signal and provide an unlock alarm signal. The second logic function circuit in the preferred embodiment of this invention is an AND gate. The lock detection circuit further includes a latching circuit in communication with the second logic function and the input reference signal to capture and retain said unlock alarm signal indicating loss of phase-frequency lock of said phase lock loop.

46. 发明授权

US07034594B2 Differential master/slave CML latch 失效
标题翻译：差分主/从CML锁存器
公开(公告)号：US07034594B2
公开(公告)日：2006-04-25
申请号：US10833605
申请日：2004-04-28
申请人： David Meltzer , Muralikumar A. Padaparambil , Tat C. Wu
发明人： David Meltzer , Muralikumar A. Padaparambil , Tat C. Wu
IPC分类号： H03K3/037
CPC分类号： H03K3/356139 , H03K3/3562
摘要： A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.
摘要翻译：全差分相位和频率检测器利用多功能差分逻辑门来实现差分和门操作，并提供完全差分D触发器。多功能差分逻辑门有四个输入，可以分为两对真和补两个信号。通过选择性地将输入重新分配给不同的信号对，可以使差分逻辑门提供同时的与/或非逻辑运算或同时的OR / NOR逻辑运算之一。差分D-触发器按照主/从配置实现，并且响应于输入时钟信号，输入复位输入和输入数据信号的真实和补码形式，并且还提供输出的真实和补充形式信号。相位和频率检测器中的所有组件都以CML电路配置为例。

47. 发明申请

US20060017731A1 Font representations 有权
公开(公告)号：US20060017731A1
公开(公告)日：2006-01-26
申请号：US10898578
申请日：2004-07-26
申请人： Tanya Matskewich , David Kilgrow , David Meltzer
发明人： Tanya Matskewich , David Kilgrow , David Meltzer
IPC分类号： G06T11/00
CPC分类号： G09G5/246
摘要： Methods for rendering font objects include: receiving input identifying an object to be rendered; selecting a data set for rendering the object from: (a) a first data set including font object data in a first format (e.g., trajectory data), and (b) a second data set including font object data in a second format (e.g., outline data); and rendering the object using the selected data set. The data set may be selected based on at least one run time parameter, such as the ppem or space available for the rendering, the desired text size, system resolution, font object complexity, contextual information, etc., to provide a high quality rendered image. Additional data sets (e.g., augmenting data, enhancing data, etc.) may be included to provide more rendering options to further increase the quality of the rendered image under some conditions. The various data sets may be independently created so that each data set can be produced specifically targeted to selected rendering conditions (such as a selected ppem range).

48. 发明授权

US06580293B1 Body-contacted and double gate-contacted differential logic circuit and method of operation 有权
标题翻译：身体接触和双门接触差分逻辑电路及其操作方法
公开(公告)号：US06580293B1
公开(公告)日：2003-06-17
申请号：US09683325
申请日：2001-12-14
申请人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
发明人： Kerry Bernstein , Peter E. Cottrell , Stephen V. Kosonocky , David Meltzer , Edward J. Nowak , Kevin J. Nowka , Norman J. Rohrer
IPC分类号： H03K19096
CPC分类号： H03K19/1737 , H03K3/356113 , H03K19/0963
摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.
摘要翻译：设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

49. 发明授权

US6138208A Multiple level cache memory with overlapped L1 and L2 memory access 失效
标题翻译：具有重叠的L1和L2存储器访问的多级高速缓存
公开(公告)号：US6138208A
公开(公告)日：2000-10-24
申请号：US59000
申请日：1998-04-13
申请人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0884
摘要： A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.
摘要翻译：提供对多个高速缓存级别的同时或重叠访问以减少对于较高级别的高速缓存未命中的延迟损失的方法。处理器发出值（数据或指令）的请求，并且在确定高速缓存的较高级别是否发生了该值的高速缓存未命中之前被转发到高速缓存的较低级。在其中较低级别是L2高速缓存的实施例中，L2高速缓存可以将该值直接提供给处理器。地址解码器在高速缓存的较高级并行操作以满足多个同时的存储器请求。其中一个地址（由基于来自高速缓存的较高级别的命中/未命中信息的优先级逻辑选择）由多路复用器选通到高速缓存的较低级的多个存储器阵列字线驱动器。可以立即解码地址中的一些不需要虚拟到实际转换的位。

50. 发明授权

US6065110A Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue 失效
标题翻译：用于加载能够无序指令发出的处理器的指令缓冲器的方法和装置
公开(公告)号：US6065110A
公开(公告)日：2000-05-16
申请号：US20631
申请日：1998-02-09
申请人： David Meltzer , Joel Abraham Silberman
发明人： David Meltzer , Joel Abraham Silberman
IPC分类号： G06F12/08 , G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： A method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue are disclosed. The processor capable of out-of-order instruction issue includes an instruction cache having multiple cache lines. The instruction cache is coupled to an instruction buffer via a multiplexor. The instruction buffer includes several slots, and these slots are sequentially filled by instructions from the instruction cache under the supervision of the multiplexor. The slot in which the first instruction resides is dictated by a fetch address. Any empty slot in the instruction buffer will be filled with instructions from a subsequent cache line of the instruction cache if the first instruction does not reside in the first slot of the instruction buffer.
摘要翻译：公开了一种用于加载能够无序指令发布的处理器的指令缓冲器的方法和装置。能够无序指令的处理器包括具有多个高速缓存行的指令高速缓存。指令高速缓存通过多路复用器耦合到指令缓冲器。指令缓冲器包括几个时隙，并且这些时隙由多路复用器的监督下的来自指令高速缓存的指令顺序地填充。第一条指令所在的时隙由取出地址决定。如果第一条指令不在指令缓冲区的第一个时隙中，指令缓冲区中的任何空的槽将被来自指令高速缓存的后续高速缓存行的指令填充。

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