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41. 发明授权

US5354703A EEPROM cell array with tight erase distribution 失效
标题翻译：具有紧密擦除分布的EEPROM单元阵列
公开(公告)号：US5354703A
公开(公告)日：1994-10-11
申请号：US85430
申请日：1993-06-29
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L27/115 , H01L21/70
CPC分类号： H01L27/115
摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11). The program and erase regions of each cell are physically separate from each other, and the characteristics of each of those regions may be made optimum independently from each other. Field oxide insulators (25) defining the channels (Ch) and the source line (17) have straight-line edges adjacent the source line (17) and adjacent the channel (Ch).
摘要翻译：在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。每个存储单元包括源（11）和漏极（12），其间具有相应的通道（Ch）。控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。通道部分（Ch）用作源（11）和漏极（12）的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。每个存储单元通过热通道从通道注入浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）到源极（11）的隧穿进行擦除。每个单元的编程和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性可以彼此独立地最优化。限定通道（Ch）和源极线（17）的场氧化物绝缘体（25）具有与源极线（17）相邻并且邻近通道（Ch）的直线边缘。

42. 发明授权

US5283203A Self-aligned contact process for complementary field-effect integrated circuits 失效
标题翻译：互补场效应集成电路的自对准接触过程
公开(公告)号：US5283203A
公开(公告)日：1994-02-01
申请号：US843705
申请日：1992-02-28
申请人： Manzur Gill , Danny Shum
发明人： Manzur Gill , Danny Shum
IPC分类号： H01L21/28 , H01L21/74 , H01L21/8238 , H01L23/485 , H01L27/092 , H01L27/115 , H01L21/265
CPC分类号： H01L21/743 , H01L23/485 , H01L27/115 , H01L2924/0002 , H01L2924/3011 , Y10S148/018 , Y10S148/133
摘要： A method for making a NMOS self-aligned contact in CMOS circuits without an extra mask is described. The maskless contact technique makes use of the fact that the blanket N-type implant, self-aligned to exposed field-oxide edge, will not change the P+ diffusion to N-type. The net P+ concentration in the contact region is reduced slightly but does not degrade the PMOS device performance.
摘要翻译：描述了在没有额外掩模的CMOS电路中制造NMOS自对准接触的方法。无掩模接触技术利用以下事实：自对准到曝光的场氧化物边缘的覆盖N型注入不会将P +扩散改变为N型。接触区域中的净P +浓度略有减小，但不会降低PMOS器件性能。

43. 发明授权

US5264718A EEPROM cell array with tight erase distribution 失效
标题翻译：具有紧密擦除分布的EEPROM单元阵列
公开(公告)号：US5264718A
公开(公告)日：1993-11-23
申请号：US925282
申请日：1992-08-06
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L27/115 , H01L29/68
CPC分类号： H01L27/115
摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11). The program and erase regions of each cell are physically separate from each other, and the characteristics of each of those regions may be made optimum independently from each other. Field oxide insulators (25) defining the channels (Ch) and the source line (17) have straight-line edges adjacent the source line (17) and adjacent the channel (Ch).
摘要翻译：在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。每个存储单元包括源（11）和漏极（12），其间具有相应的通道（Ch）。控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。通道部分（Ch）用作源（11）和漏极（12）的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。每个存储单元通过热通道从通道注入浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）到源极（11）的隧穿进行擦除。每个单元的编程和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性可以彼此独立地最优化。限定通道（Ch）和源极线（17）的场氧化物绝缘体（25）具有与源极线（17）相邻并且邻近通道（Ch）的直线边缘。

44. 发明授权

US5238855A Cross-point contact-free array with a high-density floating-gate structure 失效
标题翻译：具有高密度浮栅结构的交叉点无接触阵列
公开(公告)号：US5238855A
公开(公告)日：1993-08-24
申请号：US722729
申请日：1991-06-27
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L27/115
CPC分类号： H01L27/115
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Bitline isolation is by P/N junction or by oxide-filled trench, permitting relatively small spacing between transistors. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。位线隔离是通过P / N结或通过氧化物填充沟槽，允许晶体管之间的间隔相对较小。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过在控制栅极和浮置栅极之间使用具有相对较高介电常数的绝缘体来提高编程和擦除电压到浮栅的耦合。所得到的结构是可编程存储器单元的密集交叉点阵列。

45. 发明授权

US5120571A Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates 失效
标题翻译：具有硅化掩埋位线和单步定义浮动栅极的浮栅存储器阵列
公开(公告)号：US5120571A
公开(公告)日：1992-06-09
申请号：US637831
申请日：1991-01-07
申请人： Manzur Gill , Howard L. Tigelaar
发明人： Manzur Gill , Howard L. Tigelaar
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L29/7883 , H01L29/7886 , Y10S438/981
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The four sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。字线之间和位线之间的隔离是厚场氧化物区域。一个厚场氧化物条将每个接地导线/位线对分开。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。浮动栅极的四个侧面被定义为单个图案化步骤。所得到的结构是可编程存储器单元的密集交叉点阵列。

46. 发明授权

US07223688B2 Single level metal memory cell using chalcogenide cladding 有权
标题翻译：使用硫族化物包层的单层金属存储单元
公开(公告)号：US07223688B2
公开(公告)日：2007-05-29
申请号：US10389114
申请日：2003-03-14
申请人： Tyler A. Lowrey , Manzur Gill
发明人： Tyler A. Lowrey , Manzur Gill
IPC分类号： H01L21/3205
CPC分类号： H01L27/2409 , G11C13/0004 , G11C2213/72 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.
摘要翻译：一种包括设置在基板上的第一导体和第二导体之间的相变材料体积的装置，以及耦合到所述体积的相变材料和所述第一导体的多个电极。一种方法，包括在衬底上的第一导体上引入耦合到所述第一导体的多个电极，在所述多个电极上引入相变材料并与所述多个电极电连通，以及将第二导体相变材料并耦合到相变材料。

47. 发明授权

US5740105A Memory cell array with LOCOS free isolation 失效
标题翻译：具有LOCOS自由隔离的存储单元阵列
公开(公告)号：US5740105A
公开(公告)日：1998-04-14
申请号：US731649
申请日：1996-10-17
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/8247 , H01L27/115 , G11C11/34
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： An EPROM or flash EEPROM, which has an array of single-transistor, stacked-gate, memory cells. Active areas for transistor elements are in columns up and down the array, with columns being isolated by thick field oxide strips (220). Word lines (236) and source lines (212) run across the array. Bit lines (216) run along the active area columns to connect transistor drains (218). Bit lines are perpendicular to word lines. Each stacked gate includes a control gate (232) and a floating gate (230), with the latter having a top portion (230b) and a bottom portion (230a) that are separately deposited and etched. The bottom portion (230a) is etched in strips along the active area columns, and define the gate width of each cell. The top portion (230b) overlaps the bottom portion (230a) to improve capacitance between control gate (232) and floating gate (230).
摘要翻译： EPROM或闪存EEPROM，具有单晶体管堆叠栅极存储单元的阵列。晶体管元件的有源区域在阵列上下列，列由厚场氧化物条（220）隔离。字线（236）和源线（212）跨越阵列。位线（216）沿有源区列延伸以连接晶体管漏极（218）。位线垂直于字线。每个堆叠的栅极包括控制栅极（232）和浮动栅极（230），后者具有分开沉积和蚀刻的顶部（230b）和底部（230a）。底部（230a）沿有源区域列被蚀刻成条，并且限定每个单元的栅极宽度。顶部（230b）与底部部分（230a）重叠以改善控制栅极（232）和浮动栅极（230）之间的电容。

48. 发明授权

US5365082A MOSFET cell array 失效
标题翻译： MOSFET单元阵列
公开(公告)号：US5365082A
公开(公告)日：1994-11-15
申请号：US954223
申请日：1992-09-30
申请人： Manzur Gill , Pradeep L. Shah , Dave J. McElroy
发明人： Manzur Gill , Pradeep L. Shah , Dave J. McElroy
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/115 , H01L27/12 , H01L21/302
CPC分类号： H01L27/11521 , H01L21/76213 , H01L27/115
摘要： A CMOS memory cell array, and a process for making it, that avoids problems caused by LOCOS isolation of cells. Moats are formed by etching away columns of a thick field oxide layer. The moats have two-tiered sidewalls, such that an upper tier is sloped, and a lower tier is more vertical. This approach provides the advantages of sloped sidewalls, but avoids filament problems. After the moats are formed, subsequent fabrication steps may be in accordance with conventional fabrication techniques for CMOS arrays.
摘要翻译： CMOS存储器单元阵列及其制造方法，可以避免由于LOCOS隔离单元引起的问题。通过蚀刻掉厚场氧化物层的柱形成护壁。护城河具有双层侧壁，使得上层倾斜，并且较低层更垂直。这种方法提供了倾斜侧壁的优点，但避免了灯丝问题。在形成护城河之后，随后的制造步骤可以与CMOS阵列的常规制造技术相一致。

49. 发明授权

US5350706A CMOS memory cell array 失效
标题翻译： CMOS存储单元阵列
公开(公告)号：US5350706A
公开(公告)日：1994-09-27
申请号：US954368
申请日：1992-09-30
申请人： Dave J. McElroy , Manzur Gill , Pradeep L. Shah
发明人： Dave J. McElroy , Manzur Gill , Pradeep L. Shah
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/70
CPC分类号： H01L27/11521 , H01L27/115
摘要： A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
摘要翻译：一种CMOS存储单元阵列及其形成方法，其避免了由场氧化物四舍五入引起的问题。护城河模式定义了活动区域和场氧化物区域的交替列。源线模式定义了源行行。将硅掺杂剂注入到未被源极线图案覆盖的区域中以形成埋入的n +源极线。场氧化物区域形成在未被护套图案覆盖的区域中。随后的制造步骤可以与传统的CMOS制造技术相一致。

50. 发明授权

US5321288A Nonvolatile memory array in which each cell has a single floating gate having two tunnelling windows 失效
标题翻译：非易失性存储器阵列，其中每个单元具有具有两个隧道窗口的单个浮动栅极
公开(公告)号：US5321288A
公开(公告)日：1994-06-14
申请号：US908609
申请日：1992-06-29
申请人： Manzur Gill , Theodore D. Lindgren
发明人： Manzur Gill , Theodore D. Lindgren
IPC分类号： H01L21/336 , H01L21/8247 , H01L29/788 , H01L27/115
CPC分类号： H01L27/11521 , H01L29/66825 , H01L29/7883 , Y10S438/981
摘要： A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first and second sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.
摘要翻译：具有用于编程和擦除的分离区域的非易失性存储单元。电池在半导体本体的表面上以阵列形成，每个电池包括作为源 - 列线的一部分的源，并且包括作为漏 - 列线的一部分的漏极。每个单元在源极和漏极之间具有第一和第二子通道。每个电池单元的第一子通道的电导率由场板控制，该场板是位于第一子通道上并与第一子通道绝缘的场板 - 列 - 列线的一部分。每个第二子通道的电导率由形成在第二子通道上并与第二子通道绝缘的浮动栅极控制。每个浮动栅极具有位于相邻源极列线上方的第一隧道窗口，并且具有位于相邻排列 - 列线上方的第二隧道窗口。包括控制栅极的行线位于单元的浮动栅极的上方并与之隔绝，用于读取，编程和擦除单元。场板导体仅允许通过第一隧道窗口对单元进行编程，并且仅通过第二隧道窗口擦除单元，反之亦然。

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