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41. 发明申请

US20070195602A1 REDUCING FLOATING GATE TO FLOATING GATE COUPLING EFFECT 有权
标题翻译：降低浮动门到浮动联接效应
公开(公告)号：US20070195602A1
公开(公告)日：2007-08-23
申请号：US11735265
申请日：2007-04-13
申请人： Yupin Fong , Daniel Guterman
发明人： Yupin Fong , Daniel Guterman
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/16
摘要： For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the erase process or part of the programming operation.
摘要翻译：对于非易失性存储器系统，将擦除阈值电压分布压缩到最低阈值电压状态将降低有效数据阈值电压窗口。降低有效的数据阈值电压窗口可以将浮栅减少到浮栅耦合效应。压缩可以作为擦除过程的一部分或编程操作的一部分来执行。

42. 发明申请

US20070153577A1 Systems for alternate row-based reading and writing for non-volatile memory 有权
标题翻译：用于非易失性存储器的替代行读和写的系统
公开(公告)号：US20070153577A1
公开(公告)日：2007-07-05
申请号：US11321346
申请日：2005-12-29
申请人： Daniel Guterman
发明人： Daniel Guterman
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5622
摘要： A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines.
摘要翻译：一组存储元件从与集合的选择栅极线相邻的字线WLn开始被编程。在对第一字线进行编程之后，跳过与第一字线相邻的下一个字线WLn + 1，并对与WLn + 1相邻的下一个字线WLn + 2进行编程。然后编程WLn + 1。根据序列{WLn + 4，WLn + 3，WLn + 6，WLn + 5，...，。。 }直到所有集合的最后一个字线都被编程为止。然后编程最后一个字线。通过以这种方式进行编程，组（WLn + 1，WLn + 3等）的一些字线没有随后编程的相邻字线。这些字线的存储单元将不会经历由于随后编程的相邻存储单元而产生的任何漂浮栅极与浮栅耦合阈值电压偏移的影响。在不使用基于相邻存储器单元的偏移或补偿的情况下读取没有随后编程的邻居的字线。使用基于随后编程的相邻字线内的数据状态的补偿来读取其他字线。

43. 发明申请

US20070091681A1 Non-Volatile Memory With Improved Programming and Method Therefor 审中-公开
标题翻译：非易失性存储器具有改进的编程及其方法
公开(公告)号：US20070091681A1
公开(公告)日：2007-04-26
申请号：US11562286
申请日：2006-11-21
申请人： Geoffrey Gongwer , Daniel Guterman
发明人： Geoffrey Gongwer , Daniel Guterman
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3481 , G11C2211/5621
摘要： Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.
摘要翻译：具有诸如EEPROM和闪存EEPROM的非易失性电荷存储能力的非易失性存储器由并行应用于多个存储器单元的编程系统来编程。通过使用数据相关的编程电压以最小的编程脉冲将每个单元编程到其目标状态来实现增强的性能。通过执行多阶段中的编程操作来实现进一步的改进，其中每个连续相以更精细的编程分辨率执行，例如采用具有较温和的阶梯波形的编程电压。这些特征允许对并行编程的存储器单元组的目标状态进行快速和准确的收敛，从而允许每个单元存储几位信息而不牺牲性能。

44. 发明申请

US20070016704A1 Removable Mother/Daughter Peripheral Card 审中-公开
标题翻译：可拆卸的母亲/女儿外围卡
公开(公告)号：US20070016704A1
公开(公告)日：2007-01-18
申请号：US11463139
申请日：2006-08-08
申请人： Eliyahou Harari , Daniel Guterman , Robert Wallace
发明人： Eliyahou Harari , Daniel Guterman , Robert Wallace
IPC分类号： G06F13/12
CPC分类号： G06F13/4068 , G06K19/07741 , H05K5/0265 , H05K5/0282
摘要： A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.
摘要翻译：具有个人计算机（“PC”）卡形状因子并且可拆卸地耦合到主机系统外部的外围卡进一步被划分为母卡部分和子卡部分。子卡可拆卸地耦合到母卡。在优选实施例中，低成本闪存“软盘”是通过仅包含快闪EEPROM芯片的子卡并由驻留在母卡上的存储器控制器来控制的。本发明的其它方面包括：母卡上的综合控制器，其能够控制可连接到母卡的子卡上的预定义的一组外围设备; 将一些主机驻地硬件重定位到母卡以允许最小的主机系统; 可容纳多张子卡的母卡; 子卡也直接与具有嵌入式控制器的主机操作; 携带编码数据的子卡和用于解码的信息; 和具有安全功能的子卡。

45. 发明申请

US20060221700A1 Charge packet metering for coarse/fine programming of non-volatile memory 有权
标题翻译：充电数据包测量用于粗略/精细编程非易失性存储器
公开(公告)号：US20060221700A1
公开(公告)日：2006-10-05
申请号：US11429769
申请日：2006-05-08
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5624
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

46. 发明申请

US20060129751A1 Novel multi-state memory 有权
标题翻译：新型多状态存储器
公开(公告)号：US20060129751A1
公开(公告)日：2006-06-15
申请号：US11330923
申请日：2006-01-11
申请人： Daniel Guterman , Yupin Fong
发明人： Daniel Guterman , Yupin Fong
IPC分类号： G11C16/06 , G11C16/28 , G06F12/14
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and- self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
摘要翻译：通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更大的内存状态容限，涵盖了广泛的动态范围。对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和检测实际的最终数字数据。

47. 发明申请

US20050248988A1 Boosting to control programming of non-volatile memory 有权
标题翻译：促进控制非易失性存储器的编程
公开(公告)号：US20050248988A1
公开(公告)日：2005-11-10
申请号：US10839764
申请日：2004-05-05
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34 , G11C16/04 , G11C16/12 , G11C16/30 , G11C16/34
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C16/3459
摘要： A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings while applying the first phase of the boosting signal, and applying an inhibit level to unselected bit lines of the NAND strings while applying the first phase of the boosting signal. Subsequently, a second phase of the boosting signal is applied to the one or more unselected word lines and the signal(s) on the selected bit lines are changed by applying the inhibit level to the selected bit lines so that NAND strings associated with the selected bit lines will be boosted by the second phase of the boosting signal. A program voltage signal is applied to a selected word line in order to program storage elements connected to the selected word line.
摘要翻译：公开了一种更精确地编程非易失性存储器的系统。在一个实施例中，该系统包括将一个升压信号的第一相位应用于一组NAND串的一个或多个未选字线，将编程电平施加到NAND串的选定位线，同时施加升压信号的第一相位并且在施加升压信号的第一相位时将禁止电平施加到NAND串的未选位线。随后，将升压信号的第二相位施加到一个或多个未选字线，并且通过将所述禁止电平施加到所选择的位线来改变所选位线上的信号，使得与所选择的位线相关联的NAND串位线将由升压信号的第二阶段提升。将程序电压信号施加到所选择的字线，以便编程连接到所选字线的存储元件。

48. 发明申请

US20050226055A1 Programming inhibit for non-volatile memory 有权
标题翻译：对非易失性存储器进行编程禁止
公开(公告)号：US20050226055A1
公开(公告)日：2005-10-13
申请号：US10823421
申请日：2004-04-13
申请人： Daniel Guterman
发明人： Daniel Guterman
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/12
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, the storage elements of a NAND string are partitioned into at least two regions. A first boosting voltage is applied to the first region of the string while a second larger boosting voltage is applied to the second region. The first region includes the addressed row or selected word line for programming. The boosting voltages are applied to the NAND strings of a block while the NAND strings are being inhibited from programming. In this manner, the second boosting voltage can be made larger without inducing program disturb on the memory cells receiving the larger boosting voltage. The boosted voltage potentials of the NAND string channels are trapped within the first region by lowering the boosting voltage on one or more bounding rows. The second boosting voltage is then lowered and data is applied to the bit lines of the NAND strings to select the appropriate strings for programming. The trapped voltage potential discharges or remains in the boosted state for programming depending on whether a string is selected for programming or is to remain inhibited from programming.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，NAND串的存储元件被划分成至少两个区域。第一升压电压被施加到串的第一区域，而第二较大升压电压施加到第二区域。第一个区域包括用于编程的寻址行或所选字线。当NAND串被禁止编程时，升压电压被施加到块的NAND串。以这种方式，可以使第二升压电压更大，而不会对接收到较大升压电压的存储单元造成编程干扰。通过降低一个或多个边界行上的升压电压，NAND串通道的升压电压被捕获在第一区域内。然后降低第二升压电压，并将数据施加到NAND串的位线，以选择适当的编程串。被捕获的电压电位放电或保持在升压状态以进行编程，这取决于是否选择一个串来进行编程，或者被禁止编程。

49. 发明申请

US20050213361A1 Non-volatile memory with improved programming and method therefor 有权
标题翻译：具有改进编程及其方法的非易失性存储器
公开(公告)号：US20050213361A1
公开(公告)日：2005-09-29
申请号：US11126044
申请日：2005-05-09
申请人： Geoffrey Gongwer , Daniel Guterman
发明人： Geoffrey Gongwer , Daniel Guterman
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C17/00
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3481 , G11C2211/5621
摘要： Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.
摘要翻译：具有诸如EEPROM和闪存EEPROM的非易失性电荷存储能力的非易失性存储器由并行应用于多个存储器单元的编程系统来编程。通过使用数据相关的编程电压以最小的编程脉冲将每个单元编程到其目标状态来实现增强的性能。通过执行多阶段中的编程操作来实现进一步的改进，其中每个连续相以更精细的编程分辨率执行，例如采用具有较温和的阶梯波形的编程电压。这些特征允许对并行编程的存储器单元组的目标状态进行快速和准确的收敛，从而允许每个单元存储几位信息而不牺牲性能。

50. 发明申请

US20050083726A1 Soft errors handling EEPROM devices 失效
标题翻译：处理EEPROM设备的软错误
公开(公告)号：US20050083726A1
公开(公告)日：2005-04-21
申请号：US10974366
申请日：2004-10-26
申请人： Daniel Auclair , Jeffrey Craig , John Mangan , Robert Norman , Daniel Guterman , Sanjay Mehrotra
发明人： Daniel Auclair , Jeffrey Craig , John Mangan , Robert Norman , Daniel Guterman , Sanjay Mehrotra
IPC分类号： G06F11/10 , G11C16/10 , G11C29/50 , G11C29/52 , G11C11/00
CPC分类号： G11C29/028 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
摘要翻译：正常使用固态存储器（如EEPROM或闪存EEPROM）时会发生软错误。存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

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